JPS5692473A - Logic function tester - Google Patents

Logic function tester

Info

Publication number
JPS5692473A
JPS5692473A JP17008079A JP17008079A JPS5692473A JP S5692473 A JPS5692473 A JP S5692473A JP 17008079 A JP17008079 A JP 17008079A JP 17008079 A JP17008079 A JP 17008079A JP S5692473 A JPS5692473 A JP S5692473A
Authority
JP
Japan
Prior art keywords
terminal
signal
outputs
clock
logic function
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17008079A
Other languages
Japanese (ja)
Inventor
Shozo Toda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17008079A priority Critical patent/JPS5692473A/en
Publication of JPS5692473A publication Critical patent/JPS5692473A/en
Pending legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE: To enable testing of a wide range of logic functions to be made by selectively applying clock signals besides other input signal to an input terminal.
CONSTITUTION: A control clock generator 1 generates control clocks CK1, CK2 and CK3. The control clocks CK1WCK3 have all the same period of the test cycle. A D.FF7 with R.S outputs "1" when "0" is applied to its set terminal S, outputs "0" when "0" is applied to its reset terminal R, and outputs the signal applied to the terminal D0 by the application of the clock when "1" is applied to the set terminal S and reset terminal R, respectively. It is possible to selectively apply the general input signal and clock signal by the signal transmitted to buffers D and X.
COPYRIGHT: (C)1981,JPO&Japio
JP17008079A 1979-12-26 1979-12-26 Logic function tester Pending JPS5692473A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17008079A JPS5692473A (en) 1979-12-26 1979-12-26 Logic function tester

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17008079A JPS5692473A (en) 1979-12-26 1979-12-26 Logic function tester

Publications (1)

Publication Number Publication Date
JPS5692473A true JPS5692473A (en) 1981-07-27

Family

ID=15898262

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17008079A Pending JPS5692473A (en) 1979-12-26 1979-12-26 Logic function tester

Country Status (1)

Country Link
JP (1) JPS5692473A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5412555A (en) * 1977-06-29 1979-01-30 Takeda Riken Ind Co Ltd Waveform generator

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5412555A (en) * 1977-06-29 1979-01-30 Takeda Riken Ind Co Ltd Waveform generator

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