JPS57100537A - Arithmetic controller - Google Patents

Arithmetic controller

Info

Publication number
JPS57100537A
JPS57100537A JP55175829A JP17582980A JPS57100537A JP S57100537 A JPS57100537 A JP S57100537A JP 55175829 A JP55175829 A JP 55175829A JP 17582980 A JP17582980 A JP 17582980A JP S57100537 A JPS57100537 A JP S57100537A
Authority
JP
Japan
Prior art keywords
external device
switching
arithmetic processor
memory
arithmetic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55175829A
Other languages
Japanese (ja)
Inventor
Shuichi Hara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP55175829A priority Critical patent/JPS57100537A/en
Publication of JPS57100537A publication Critical patent/JPS57100537A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To obtain an arithmetic controller which can process a system requiring a control program having the storage capacity more than that of an arithmetic processor, by providing a switching/connecting means between the arithmetic processor and plural memories incorporating a control program of each external device. CONSTITUTION:Plural memories storing the control programs of prescribed plural external devices are connected to an arithmetic processor via a switching/ connecting means. Thus a selective connection is possible in accordance with the type of the external device to be connected. For instance, the flag information ''0'' or ''1'' of a connected external device DA or DB is read out of a flag information generating means F by an arithmetic processor MPU and sent to a switching/connecting means SW via a switch control means SWC to be applied to the selection terminal of a memory MB from the means SW as well as to the selection terminal of a memory MA via an inverting circuit N. In such a way, the processor MPU is connected to a memory corresponding to a connected external device.
JP55175829A 1980-12-15 1980-12-15 Arithmetic controller Pending JPS57100537A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55175829A JPS57100537A (en) 1980-12-15 1980-12-15 Arithmetic controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55175829A JPS57100537A (en) 1980-12-15 1980-12-15 Arithmetic controller

Publications (1)

Publication Number Publication Date
JPS57100537A true JPS57100537A (en) 1982-06-22

Family

ID=16002942

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55175829A Pending JPS57100537A (en) 1980-12-15 1980-12-15 Arithmetic controller

Country Status (1)

Country Link
JP (1) JPS57100537A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5092653A (en) * 1973-12-14 1975-07-24
JPS5540438B2 (en) * 1974-03-30 1980-10-17

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5092653A (en) * 1973-12-14 1975-07-24
JPS5540438B2 (en) * 1974-03-30 1980-10-17

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