JPS57100767A - Mos type semiconductor device - Google Patents

Mos type semiconductor device

Info

Publication number
JPS57100767A
JPS57100767A JP55177492A JP17749280A JPS57100767A JP S57100767 A JPS57100767 A JP S57100767A JP 55177492 A JP55177492 A JP 55177492A JP 17749280 A JP17749280 A JP 17749280A JP S57100767 A JPS57100767 A JP S57100767A
Authority
JP
Japan
Prior art keywords
type
region
semiconductor device
substrate
type semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55177492A
Other languages
Japanese (ja)
Inventor
Hideji Koike
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55177492A priority Critical patent/JPS57100767A/en
Publication of JPS57100767A publication Critical patent/JPS57100767A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/854—Complementary IGFETs, e.g. CMOS comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a MOS type semiconductor device eliminating latch up and other malfunction by a method wherein a circuit trapping unnecessary carriers created in a substrate by the overshoot or undershoot of input/output pins is provided. CONSTITUTION:A p<-> type well region 22 is formed on an n<-> type silicon substrate 21, and an n<-> type source region 23 and an n<-> type drain region 24 are formed. Furthermore, a gate electrode 26 is formed on a channel region through a gate oxide film 25 to form an n channel transistor. Meanwhile, a p<+> type source region 23' and a p<+> type drain region 24' are formed on the n<-> type substrate and a gate electrode 26' is provided through an insulating film 25' to form a p channel transistor. A p<-> type carrier trap region 28 is formed between the p<+> type drain region 24' and the p<-> type well region and the region 28 is connected to ground.
JP55177492A 1980-12-16 1980-12-16 Mos type semiconductor device Pending JPS57100767A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55177492A JPS57100767A (en) 1980-12-16 1980-12-16 Mos type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55177492A JPS57100767A (en) 1980-12-16 1980-12-16 Mos type semiconductor device

Publications (1)

Publication Number Publication Date
JPS57100767A true JPS57100767A (en) 1982-06-23

Family

ID=16031841

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55177492A Pending JPS57100767A (en) 1980-12-16 1980-12-16 Mos type semiconductor device

Country Status (1)

Country Link
JP (1) JPS57100767A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1984001241A1 (en) * 1982-09-20 1984-03-29 Semi Processes Inc Cmos integrated circuit with guard bands for latch-up protection
JPS6083362A (en) * 1983-10-14 1985-05-11 Hitachi Ltd semiconductor equipment

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1984001241A1 (en) * 1982-09-20 1984-03-29 Semi Processes Inc Cmos integrated circuit with guard bands for latch-up protection
JPS6083362A (en) * 1983-10-14 1985-05-11 Hitachi Ltd semiconductor equipment

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