JPS57106929A - Response timing control circuit of interface operation testing device - Google Patents

Abstract

PURPOSE:To set various kinds of timing time by one testing device by providing the 1st and 2nd timing time generating circuit groups which have an a plurality of delay time and times widths. CONSTITUTION:When an interface signal (a) is applied to a monostable miltivibrator 1 which generates timing for delay time, triggering successively from the monostable multivibrator 1 to a monostable multivibrator 2, from the monostable multivibrator 2 to a monostable multivibrator 3, etc., is performed, and the respective monostable multivibrators generate and apply pulses with widths T11-T1m to a selector 23. The selector 23 adds the timing pulses from the respective monostable multivibrators to select the output of one monostable multivibrator which corresponds to a selection signal S1 from a register 21 for setting delay time timing, thereby applying to the following monostable multivibrators 11-18. The monostable multivibrators 11-18 apply pulse signals with pulse widths T21-T2m to a selector 24. The selector 24 inputs a signal S2 from a register 22 for setting timing time to select one timing signal with the prescribed pulse width as an interface output signal.