JPS57106929A - Response timing control circuit of interface operation testing device - Google Patents

Response timing control circuit of interface operation testing device

Info

Publication number
JPS57106929A
JPS57106929A JP55183343A JP18334380A JPS57106929A JP S57106929 A JPS57106929 A JP S57106929A JP 55183343 A JP55183343 A JP 55183343A JP 18334380 A JP18334380 A JP 18334380A JP S57106929 A JPS57106929 A JP S57106929A
Authority
JP
Japan
Prior art keywords
timing
monostable
selector
signal
monostable multivibrator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55183343A
Other languages
English (en)
Inventor
Kenichi Kagaya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55183343A priority Critical patent/JPS57106929A/ja
Publication of JPS57106929A publication Critical patent/JPS57106929A/ja
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP55183343A 1980-12-24 1980-12-24 Response timing control circuit of interface operation testing device Pending JPS57106929A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55183343A JPS57106929A (en) 1980-12-24 1980-12-24 Response timing control circuit of interface operation testing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55183343A JPS57106929A (en) 1980-12-24 1980-12-24 Response timing control circuit of interface operation testing device

Publications (1)

Publication Number Publication Date
JPS57106929A true JPS57106929A (en) 1982-07-03

Family

ID=16134059

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55183343A Pending JPS57106929A (en) 1980-12-24 1980-12-24 Response timing control circuit of interface operation testing device

Country Status (1)

Country Link
JP (1) JPS57106929A (ja)

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