JPS57111475A - Memory test system - Google Patents

Memory test system

Info

Publication number
JPS57111475A
JPS57111475A JP55187786A JP18778680A JPS57111475A JP S57111475 A JPS57111475 A JP S57111475A JP 55187786 A JP55187786 A JP 55187786A JP 18778680 A JP18778680 A JP 18778680A JP S57111475 A JPS57111475 A JP S57111475A
Authority
JP
Japan
Prior art keywords
signal
period
during
nonexecution
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55187786A
Other languages
Japanese (ja)
Inventor
Shigeru Mukogasa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55187786A priority Critical patent/JPS57111475A/en
Publication of JPS57111475A publication Critical patent/JPS57111475A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To enable a test of the influence of switching, etc., by a signal during a nonexecution period, by testing a memory during the nonexecution period by using a disturbing signal which does not synchronize with a timing signal. CONSTITUTION:When a switch SW1 is connected to an H-level terminal where a timing signal is at a high level during an ineffective period, an AND gate 3 is controlled to add a disturbing signal, which does not synchronize with a timing signal from a variable frequency oscillator 1, to the ineffective part of an address timing signal through an OR circuit 5, an exclusive OR circuit 17, etc., thereby obtaining the address waveform of memory write data. Similarly, chip selection timing is controlled to test a memory by the disturbing signal, which does not synchronize with the timing signal, during a nonexecution period, thereby testing the influence of the switching, skew, noise, etc., of a signal during the nonexecution period upon the memory.
JP55187786A 1980-12-29 1980-12-29 Memory test system Pending JPS57111475A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55187786A JPS57111475A (en) 1980-12-29 1980-12-29 Memory test system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55187786A JPS57111475A (en) 1980-12-29 1980-12-29 Memory test system

Publications (1)

Publication Number Publication Date
JPS57111475A true JPS57111475A (en) 1982-07-10

Family

ID=16212193

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55187786A Pending JPS57111475A (en) 1980-12-29 1980-12-29 Memory test system

Country Status (1)

Country Link
JP (1) JPS57111475A (en)

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