JPS5715455A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5715455A
JPS5715455A JP8948980A JP8948980A JPS5715455A JP S5715455 A JPS5715455 A JP S5715455A JP 8948980 A JP8948980 A JP 8948980A JP 8948980 A JP8948980 A JP 8948980A JP S5715455 A JPS5715455 A JP S5715455A
Authority
JP
Japan
Prior art keywords
chips
monitor
function
dimensional
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8948980A
Other languages
Japanese (ja)
Inventor
Junji Sakurai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8948980A priority Critical patent/JPS5715455A/en
Publication of JPS5715455A publication Critical patent/JPS5715455A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/926—Multiple bond pads having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To facilitate the evaluation of processing function and circuit function in a three-dimensional IC by forming a function inspecting monitor at each of element forming regions formed in a multilayer via insulating layers and exposing the measurement pad of the monitor. CONSTITUTION:Chips 1a-1c formed, for example, with MOSICs are covered with PSG film 5, are laminated with an adhesive layer 6 of silicone resin or the like, and are thus secured to form a three-dimensional LSI. A simple circuit function inspecting monitor circuit of flip-flop or the like and a processing function inspecting monitor element are formed in each of these chips, and their measuring pads 2, 3 are disposed similarly to the IC pad 4 at the peripheral edge of each of the chips. The chips are reduced in size smaller at the upper layer so that the respective pad forming regions are exposed on the surface of laminated three-dimensional device. Thus, the measurement inspection, e.g., function evaluation of each chip, influence of multilayer formation, variation in the performance by environmental tests or the like can be facilitated, the yield and the reliability can be improved.
JP8948980A 1980-07-01 1980-07-01 Semiconductor device Pending JPS5715455A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8948980A JPS5715455A (en) 1980-07-01 1980-07-01 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8948980A JPS5715455A (en) 1980-07-01 1980-07-01 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5715455A true JPS5715455A (en) 1982-01-26

Family

ID=13972155

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8948980A Pending JPS5715455A (en) 1980-07-01 1980-07-01 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5715455A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5890766A (en) * 1981-11-25 1983-05-30 Mitsubishi Electric Corp Semiconductor device of multi-layer structure
JPS5912212U (en) * 1982-07-14 1984-01-25 株式会社安川電機 breaker contact
JPS5965474A (en) * 1982-09-08 1984-04-13 テキサス・インスツルメンツ・インコ−ポレイテツド Focal surface array structure and method of producing same
US4500905A (en) * 1981-09-30 1985-02-19 Tokyo Shibaura Denki Kabushiki Kaisha Stacked semiconductor device with sloping sides
JPH02220454A (en) * 1988-12-22 1990-09-03 Internatl Business Mach Corp <Ibm> Apparatus having process monitor for thin film wiring and method of process monitoring
US5818114A (en) * 1995-05-26 1998-10-06 Hewlett-Packard Company Radially staggered bond pad arrangements for integrated circuit pad circuitry
US6593663B2 (en) * 2001-07-06 2003-07-15 Denso Corporation Electronic device including stacked microchips
US7755204B2 (en) 2002-05-08 2010-07-13 Micron Technology, Inc. Stacked die module including multiple adhesives that cure at different temperatures

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4500905A (en) * 1981-09-30 1985-02-19 Tokyo Shibaura Denki Kabushiki Kaisha Stacked semiconductor device with sloping sides
JPS5890766A (en) * 1981-11-25 1983-05-30 Mitsubishi Electric Corp Semiconductor device of multi-layer structure
JPS5912212U (en) * 1982-07-14 1984-01-25 株式会社安川電機 breaker contact
JPS5965474A (en) * 1982-09-08 1984-04-13 テキサス・インスツルメンツ・インコ−ポレイテツド Focal surface array structure and method of producing same
JPH02220454A (en) * 1988-12-22 1990-09-03 Internatl Business Mach Corp <Ibm> Apparatus having process monitor for thin film wiring and method of process monitoring
US5818114A (en) * 1995-05-26 1998-10-06 Hewlett-Packard Company Radially staggered bond pad arrangements for integrated circuit pad circuitry
US6593663B2 (en) * 2001-07-06 2003-07-15 Denso Corporation Electronic device including stacked microchips
US7755204B2 (en) 2002-05-08 2010-07-13 Micron Technology, Inc. Stacked die module including multiple adhesives that cure at different temperatures

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