JPS57183142A - Preholding circuit - Google Patents

Preholding circuit

Info

Publication number
JPS57183142A
JPS57183142A JP6855581A JP6855581A JPS57183142A JP S57183142 A JPS57183142 A JP S57183142A JP 6855581 A JP6855581 A JP 6855581A JP 6855581 A JP6855581 A JP 6855581A JP S57183142 A JPS57183142 A JP S57183142A
Authority
JP
Japan
Prior art keywords
input terminals
circuit
memory
errors
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6855581A
Other languages
Japanese (ja)
Other versions
JPH0325973B2 (en
Inventor
Masayuki Ishida
Takeshi Onishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6855581A priority Critical patent/JPS57183142A/en
Publication of JPS57183142A publication Critical patent/JPS57183142A/en
Publication of JPH0325973B2 publication Critical patent/JPH0325973B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B14/00—Transmission systems not characterised by the medium used for transmission
    • H04B14/02—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
    • H04B14/04—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation using pulse code modulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
  • Noise Elimination (AREA)

Abstract

PURPOSE:To simplify the constitution of a preholdig circuit by counting the total number of errors in one block before extracting a sampled signal word to be transferred from a memory, and then using the count result and information on the word error of the memory. CONSTITUTION:An L-channel signal (a) from a data storage memory is applied to the parallel input terminals of a shift register 27 through a gate 26, and an R-channel signal (b) is supplied to the parallel input terminals of a shift register 30 through a gate 28. A detecting circuit 29 counts the total number of errors in eight words in one sampled signal word block and, when it is >=3, applies a corrected code, led to an output terminal 23 through a selector 20 and an exclusive OR circuit 21, to the serial input terminals of the shift registers 27 and 30. When error information is supplied from an input terminal 14 to close the gates 26 and 28, the code applied to the serial input terminals is led out as an output.
JP6855581A 1981-05-07 1981-05-07 Preholding circuit Granted JPS57183142A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6855581A JPS57183142A (en) 1981-05-07 1981-05-07 Preholding circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6855581A JPS57183142A (en) 1981-05-07 1981-05-07 Preholding circuit

Publications (2)

Publication Number Publication Date
JPS57183142A true JPS57183142A (en) 1982-11-11
JPH0325973B2 JPH0325973B2 (en) 1991-04-09

Family

ID=13377118

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6855581A Granted JPS57183142A (en) 1981-05-07 1981-05-07 Preholding circuit

Country Status (1)

Country Link
JP (1) JPS57183142A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5476214A (en) * 1977-11-30 1979-06-18 Toshiba Corp Error correction apparatus
JPS55163929A (en) * 1979-06-08 1980-12-20 Victor Co Of Japan Ltd Pcm signal processing system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5476214A (en) * 1977-11-30 1979-06-18 Toshiba Corp Error correction apparatus
JPS55163929A (en) * 1979-06-08 1980-12-20 Victor Co Of Japan Ltd Pcm signal processing system

Also Published As

Publication number Publication date
JPH0325973B2 (en) 1991-04-09

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