JPS6482821A - System and device for sequential decoding - Google Patents

Abstract

PURPOSE:To widely reduce the number of times of metric operation by serially constituting a shift register, combining a time-varying decoding registering part to fix a tap and a dummy bit inserting pattern or using a time varying convolution coder. CONSTITUTION:An algorithm control part 60 sends an instruction to read a receiving series corresponding to the branch to be tried at present to an input output buffer memory part 10, and by receiving this, the input output buffer memory part 10 sends the receiving data series to the said branch from a read ing channel 11 toward a metric arithmetic part 50. On the when the said branch is composed of an information bit and a parity bit, a reading instruction is issued from the algorithm control part 60 to a reading channel 11 twice. After the signals are serially/parallelly converted in a serial parallel converting circuit 51, they enters comparators 52 and 53. When the said branch is composed of a parity bit only, first, a switch 81 is switched to an SW2 side, and after a dummy symbol corresponding to the information bit is sent, a parity receiving bit is transferred through the reading channel 11 to the serial parallel converting circuit 51.