JPS57196616A - Timing controlling circuit - Google Patents

Timing controlling circuit

Info

Publication number
JPS57196616A
JPS57196616A JP56080117A JP8011781A JPS57196616A JP S57196616 A JPS57196616 A JP S57196616A JP 56080117 A JP56080117 A JP 56080117A JP 8011781 A JP8011781 A JP 8011781A JP S57196616 A JPS57196616 A JP S57196616A
Authority
JP
Japan
Prior art keywords
signal
circuit
output signal
input
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56080117A
Other languages
Japanese (ja)
Inventor
Seijiro Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56080117A priority Critical patent/JPS57196616A/en
Publication of JPS57196616A publication Critical patent/JPS57196616A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/64—Generators producing trains of pulses, i.e. finite sequences of pulses

Landscapes

  • Stopping Of Electric Motors (AREA)

Abstract

PURPOSE:To simplify a circuit and to make the entire circuit of a control system compact, by constituting the circuit with one delay element, one flip-flop and several logical gates. CONSTITUTION:An FF31 is set with the 1st control signal, that is, MOTOR- START signal and reset with the 2nd control signal, that is, the MOTOR-STOP signal. An exclusive logical sum circuit 32 takes a signal delaying and inverting an output signal from a terminal Q of the FF31 at a delay element 33 as an input signal. The 1st NAND logical operation circuit 35 takes a signal obtained from the output signal from the terminal Q of the FF31 through delay and inversion as one input and the output signal from the circuit 32 as another input. In the 2nd NAND logical operating circuit 37, a signal obtained from the output signal at the terminal Q of the FF31 is taken as one input and the output signal of the circuit 32 is taken as another input.
JP56080117A 1981-05-28 1981-05-28 Timing controlling circuit Pending JPS57196616A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56080117A JPS57196616A (en) 1981-05-28 1981-05-28 Timing controlling circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56080117A JPS57196616A (en) 1981-05-28 1981-05-28 Timing controlling circuit

Publications (1)

Publication Number Publication Date
JPS57196616A true JPS57196616A (en) 1982-12-02

Family

ID=13709245

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56080117A Pending JPS57196616A (en) 1981-05-28 1981-05-28 Timing controlling circuit

Country Status (1)

Country Link
JP (1) JPS57196616A (en)

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