JPS6484343A - Interruption control circuit - Google Patents

Interruption control circuit

Info

Publication number
JPS6484343A
JPS6484343A JP62243084A JP24308487A JPS6484343A JP S6484343 A JPS6484343 A JP S6484343A JP 62243084 A JP62243084 A JP 62243084A JP 24308487 A JP24308487 A JP 24308487A JP S6484343 A JPS6484343 A JP S6484343A
Authority
JP
Japan
Prior art keywords
interruption
signal
input
interruption signal
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62243084A
Other languages
Japanese (ja)
Inventor
Kenji Nozawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Japan Inc
Original Assignee
Yokogawa Hewlett Packard Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Hewlett Packard Ltd filed Critical Yokogawa Hewlett Packard Ltd
Priority to JP62243084A priority Critical patent/JPS6484343A/en
Publication of JPS6484343A publication Critical patent/JPS6484343A/en
Pending legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To improve the working efficiency of system debugging or the like attending with an operation started by an interruption by counting up interruption signals and selectively transmitting an interruption signal to an emulation CPU based on a counted value. CONSTITUTION:An input interruption signal from a target system is applied to the clock input of a flip flop (FF) 13 through an inverter 11 to set up the FF 13. At the time of detecting the leading edge of the FF 13, an interruption controlling CPU 15 applies a clear signal to the FF 13 to return the FF 13 to a reset state. The number of times of leading edges counted and, the value of a disable signal to be applied to an OR gate 17 is determined based on the counted value and whether the input interruption signal is to be passed as on output interruption signal or not is controlled. Consequently, whether the operation of a program is executed in accordance with its purpose or not can be confirmed.
JP62243084A 1987-09-28 1987-09-28 Interruption control circuit Pending JPS6484343A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62243084A JPS6484343A (en) 1987-09-28 1987-09-28 Interruption control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62243084A JPS6484343A (en) 1987-09-28 1987-09-28 Interruption control circuit

Publications (1)

Publication Number Publication Date
JPS6484343A true JPS6484343A (en) 1989-03-29

Family

ID=17098542

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62243084A Pending JPS6484343A (en) 1987-09-28 1987-09-28 Interruption control circuit

Country Status (1)

Country Link
JP (1) JPS6484343A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5375421A (en) * 1993-12-06 1994-12-27 Hsieh; Chi-Sheng Portable thermoelectric dehumidifier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5375421A (en) * 1993-12-06 1994-12-27 Hsieh; Chi-Sheng Portable thermoelectric dehumidifier

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