JPS57199252A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS57199252A
JPS57199252A JP56085222A JP8522281A JPS57199252A JP S57199252 A JPS57199252 A JP S57199252A JP 56085222 A JP56085222 A JP 56085222A JP 8522281 A JP8522281 A JP 8522281A JP S57199252 A JPS57199252 A JP S57199252A
Authority
JP
Japan
Prior art keywords
collector
layer
base
terminals
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56085222A
Other languages
Japanese (ja)
Inventor
Tadashi Hirao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56085222A priority Critical patent/JPS57199252A/en
Publication of JPS57199252A publication Critical patent/JPS57199252A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/65—Integrated injection logic

Landscapes

  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

PURPOSE:To make gate speed at each output terminal faster and make each speed equal by a method wherein a plurality of collector regios and collector output terminals are laid next to base input terminals on the same line in a base region and a couple of such systems are laid parallel facting each other. CONSTITUTION:A p type base layer 2 of a horizontal type n-p-n transistor of a semiconductor integrated circuit device which composes an integrated injection logic circuit is so arranged to face an emitter p<+> layer 6 of the n-p-n transistor. Then collector regions 1a, 1b and 1c and output terminals 4a, 4b and 4c of a collector region 1 are formed on the base layer 2 in such a manner that those respective regions and terminals are laid parallel to the p<+> layer 6 with respective base input terminals 5a, 5b and 5c in between.
JP56085222A 1981-06-01 1981-06-01 Semiconductor integrated circuit device Pending JPS57199252A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56085222A JPS57199252A (en) 1981-06-01 1981-06-01 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56085222A JPS57199252A (en) 1981-06-01 1981-06-01 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS57199252A true JPS57199252A (en) 1982-12-07

Family

ID=13852534

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56085222A Pending JPS57199252A (en) 1981-06-01 1981-06-01 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS57199252A (en)

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