JPS57201338A - Pulse generator - Google Patents

Pulse generator

Info

Publication number
JPS57201338A
JPS57201338A JP56085391A JP8539181A JPS57201338A JP S57201338 A JPS57201338 A JP S57201338A JP 56085391 A JP56085391 A JP 56085391A JP 8539181 A JP8539181 A JP 8539181A JP S57201338 A JPS57201338 A JP S57201338A
Authority
JP
Japan
Prior art keywords
circuit
pulse
output value
converter
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56085391A
Other languages
Japanese (ja)
Inventor
Toshio Sudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56085391A priority Critical patent/JPS57201338A/en
Publication of JPS57201338A publication Critical patent/JPS57201338A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/06—Frequency or rate modulation, i.e. PFM or PRM

Abstract

PURPOSE:To obtain a pulse generating circuit which can control intermittent time without the influence of the change of power voltage, the deviation of circuit elements, etc. by composing the whole circuit of ligical circuits. CONSTITUTION:When an output value of a binary counter 5 coincides with an output value of an AD converter 3, an output (a) of a coincidence circuit 4 is turned to ''1'' and a pulse signal (e) with pulse width T is generated from a single width pulse generating circuit 7. Consequently, an AD conversion start signal generating circuit 6 is actuated, an AD conversion circuit 3 starts AD conversion and the output value is set up to the suceeding value. When the pulse signal (e) ends, a differential pulse is outputted from a differentiating circuit 9, the counter 5 is returned to reset status and starts to count clock pulses again. When the output value of the counter 5 coincides with that of the AD converter 3 again, the pulse signal (e) with pulse width T is outputted. Thus, the intermittent time of pulses can be controlled by optionally setting up the output value of the AD converter 3.
JP56085391A 1981-06-03 1981-06-03 Pulse generator Pending JPS57201338A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56085391A JPS57201338A (en) 1981-06-03 1981-06-03 Pulse generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56085391A JPS57201338A (en) 1981-06-03 1981-06-03 Pulse generator

Publications (1)

Publication Number Publication Date
JPS57201338A true JPS57201338A (en) 1982-12-09

Family

ID=13857454

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56085391A Pending JPS57201338A (en) 1981-06-03 1981-06-03 Pulse generator

Country Status (1)

Country Link
JP (1) JPS57201338A (en)

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