JPS5730181A - Control system for buffer invalidation - Google Patents

Control system for buffer invalidation

Info

Publication number
JPS5730181A
JPS5730181A JP10470380A JP10470380A JPS5730181A JP S5730181 A JPS5730181 A JP S5730181A JP 10470380 A JP10470380 A JP 10470380A JP 10470380 A JP10470380 A JP 10470380A JP S5730181 A JPS5730181 A JP S5730181A
Authority
JP
Japan
Prior art keywords
address
access request
buffer invalidation
buffer
request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10470380A
Other languages
English (en)
Inventor
Shigeru Fujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10470380A priority Critical patent/JPS5730181A/ja
Publication of JPS5730181A publication Critical patent/JPS5730181A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP10470380A 1980-07-29 1980-07-29 Control system for buffer invalidation Pending JPS5730181A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10470380A JPS5730181A (en) 1980-07-29 1980-07-29 Control system for buffer invalidation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10470380A JPS5730181A (en) 1980-07-29 1980-07-29 Control system for buffer invalidation

Publications (1)

Publication Number Publication Date
JPS5730181A true JPS5730181A (en) 1982-02-18

Family

ID=14387834

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10470380A Pending JPS5730181A (en) 1980-07-29 1980-07-29 Control system for buffer invalidation

Country Status (1)

Country Link
JP (1) JPS5730181A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02133626A (ja) * 1988-11-10 1990-05-22 Toray Ind Inc 異色効果を有する毛羽糸

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02133626A (ja) * 1988-11-10 1990-05-22 Toray Ind Inc 異色効果を有する毛羽糸

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