JPS6491255A - Memory controller - Google Patents

Abstract

PURPOSE:To prevent a read request from being kept waiting and to improve performance by separating the detection of the use state of a bank which is the request destination of a write request and the read request from a controller into a memory so as to execute said detection in parallel. CONSTITUTION:At the time of the read request from the controller 2, a band busy check circuit 13 checks whether a bank is busy. When the bank is not busy, the read request is outputted to a priority decision circuit 15. When the priority is decided to be high, an access for the memory 3 is executed, and data is read from the bank of the memory 3 which the read address designates. At the time of the write request from the processor 2, a bank busy check circuit 14 checks the write address whether the bank is busy or not. When the bank is not busy, the write request is transmitted to the priority decision circuit 15. When the priority is decided to be high, data is written into the bank of the memory 3 which the write address designates.