JPS5730342A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5730342A
JPS5730342A JP10447680A JP10447680A JPS5730342A JP S5730342 A JPS5730342 A JP S5730342A JP 10447680 A JP10447680 A JP 10447680A JP 10447680 A JP10447680 A JP 10447680A JP S5730342 A JPS5730342 A JP S5730342A
Authority
JP
Japan
Prior art keywords
oxide film
stepped section
semiconductor substrate
etching
1mum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10447680A
Other languages
Japanese (ja)
Other versions
JPS6117144B2 (en
Inventor
Toshinobu Yanase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP10447680A priority Critical patent/JPS5730342A/en
Publication of JPS5730342A publication Critical patent/JPS5730342A/en
Publication of JPS6117144B2 publication Critical patent/JPS6117144B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/191—Preparing SOI wafers using full isolation by porous oxide silicon [FIPOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To bring the level measurements of an element isolation region to zero and to contrive high density integration by a method wherein a stepped section is provided by performing an etching on a semiconductor substrate and a field oxide film is formed vertically on the inner wall of the stepped section. CONSTITUTION:The pattern of an Si oxide film 2 of 1mum in thickness is formed on the Si semiconductor substrate 1, a reactive ion etching is performed using the above pattern as a mask and the stepped section 15 of 1mum in depth is formed on the semiconductor substrate 1. Then, after the Si oxide film has been removed, an ion is implanted vertically on a proton and a donor layer 16 is formed on the upper surface of the semiconductor substrate 1 and on the bottom surface of the stepped section 15. Subsequently, when anode formation is performed, no current is applied to the donor layer 16, anode is formed only on P type inner wall 15a of the stepped section 15 and a porous Si layer 17 is formed. Lastly, when a wet thermal oxidization is performed and the thin oxide film formed on the surface is removed by etching, element forming regions 7a-7c which are isolated by a field oxide film 5 can be obtained.
JP10447680A 1980-07-30 1980-07-30 Manufacture of semiconductor device Granted JPS5730342A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10447680A JPS5730342A (en) 1980-07-30 1980-07-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10447680A JPS5730342A (en) 1980-07-30 1980-07-30 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5730342A true JPS5730342A (en) 1982-02-18
JPS6117144B2 JPS6117144B2 (en) 1986-05-06

Family

ID=14381616

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10447680A Granted JPS5730342A (en) 1980-07-30 1980-07-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5730342A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6386467A (en) * 1986-09-30 1988-04-16 Toshiba Corp Semiconductor device
JP2007294857A (en) * 2006-03-28 2007-11-08 Elpida Memory Inc Semiconductor device and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6386467A (en) * 1986-09-30 1988-04-16 Toshiba Corp Semiconductor device
JP2007294857A (en) * 2006-03-28 2007-11-08 Elpida Memory Inc Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
JPS6117144B2 (en) 1986-05-06

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