JPS573125A - Data transfer controlling system - Google Patents

Data transfer controlling system

Info

Publication number
JPS573125A
JPS573125A JP7617680A JP7617680A JPS573125A JP S573125 A JPS573125 A JP S573125A JP 7617680 A JP7617680 A JP 7617680A JP 7617680 A JP7617680 A JP 7617680A JP S573125 A JPS573125 A JP S573125A
Authority
JP
Japan
Prior art keywords
bus
transfer
switch
dma
selecting switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7617680A
Other languages
Japanese (ja)
Inventor
Mitsuru Kuga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7617680A priority Critical patent/JPS573125A/en
Publication of JPS573125A publication Critical patent/JPS573125A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To switch transfer busses selectively, by providing a bus selecting switch to switch transfer busses selectively and by causing a direct memory access device to operate the transfer bus selecting switch at the autoload completion time. CONSTITUTION:When a data frame 40 reaches a transmission control interface adapter 33 through a transmission line 37, a direct memory access device (DMAC) 32 DMA-transfers the first data field 41 to the first local memory 12 through a DMA bus and a bus selecting switch 31. When autoload is performed simultaneously with transfer completion, a bus is selected by a signal line 35, and the bus selecting switch 31 is switched to be connected to the second local memory 22, and the second data field 42 is DMA-transferred to the second local memory 22 in the same manner.
JP7617680A 1980-06-06 1980-06-06 Data transfer controlling system Pending JPS573125A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7617680A JPS573125A (en) 1980-06-06 1980-06-06 Data transfer controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7617680A JPS573125A (en) 1980-06-06 1980-06-06 Data transfer controlling system

Publications (1)

Publication Number Publication Date
JPS573125A true JPS573125A (en) 1982-01-08

Family

ID=13597787

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7617680A Pending JPS573125A (en) 1980-06-06 1980-06-06 Data transfer controlling system

Country Status (1)

Country Link
JP (1) JPS573125A (en)

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