JPS573149A - Data processing device - Google Patents

Data processing device

Info

Publication number
JPS573149A
JPS573149A JP7581480A JP7581480A JPS573149A JP S573149 A JPS573149 A JP S573149A JP 7581480 A JP7581480 A JP 7581480A JP 7581480 A JP7581480 A JP 7581480A JP S573149 A JPS573149 A JP S573149A
Authority
JP
Japan
Prior art keywords
execution
register
counter
instruction
interrupt time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7581480A
Other languages
Japanese (ja)
Inventor
Sakae Otake
Mamoru Yura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7581480A priority Critical patent/JPS573149A/en
Publication of JPS573149A publication Critical patent/JPS573149A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To eliminate needless key operations to shorten the debug processing time considerably, by interrupting the execution for a prescribed instruction temporarily and by providing a means which determines this execution interrupt time. CONSTITUTION:The number of execution steps and the interrupt time are set in an execution instruction number register 7 and an interrupt time set register 12. When instructions are executed, a CPU executes a prescribed processing on a basis of instruction data read out from a ROM and transmits the result to an output part 3. The value of an instruction execution number counter 5 is compared with contents set in the register 7 by a comparator 6; and if they coincide with each other, the counter 5 is reset. Further, this coincidence signal is inputted to a stop signal generating part 8 and an interrupt time counter 10 to start the count operation. The value of the time counter 10 is compared with the value of the register 12; and if they coincide with each other, a coincidence signal is outputted from a comparing part 11, and the CPU stop signal of a control part 8 is released to return the CPU to the execution state.
JP7581480A 1980-06-05 1980-06-05 Data processing device Pending JPS573149A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7581480A JPS573149A (en) 1980-06-05 1980-06-05 Data processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7581480A JPS573149A (en) 1980-06-05 1980-06-05 Data processing device

Publications (1)

Publication Number Publication Date
JPS573149A true JPS573149A (en) 1982-01-08

Family

ID=13587018

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7581480A Pending JPS573149A (en) 1980-06-05 1980-06-05 Data processing device

Country Status (1)

Country Link
JP (1) JPS573149A (en)

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