JPS5733414A - Coding and decoding system of binary data - Google Patents

Coding and decoding system of binary data

Info

Publication number
JPS5733414A
JPS5733414A JP10869880A JP10869880A JPS5733414A JP S5733414 A JPS5733414 A JP S5733414A JP 10869880 A JP10869880 A JP 10869880A JP 10869880 A JP10869880 A JP 10869880A JP S5733414 A JPS5733414 A JP S5733414A
Authority
JP
Japan
Prior art keywords
supplied
clock
outputs
data
delivered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10869880A
Other languages
Japanese (ja)
Other versions
JPS634268B2 (en
Inventor
Teruo Furukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP10869880A priority Critical patent/JPS5733414A/en
Publication of JPS5733414A publication Critical patent/JPS5733414A/en
Publication of JPS634268B2 publication Critical patent/JPS634268B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To improve the minimum magnetizing verse interval and the demodulated phase margin, by converting the original binary data series into a binary code series suited for recording. CONSTITUTION:The original data and the original data clock are supplied to input terminals 2 and 1, respectively. The input data is delayed by a shift register 3 and delivered to outputs QA-QH. At the same time, the common clock which is used for conversion is supplied to an input terminal 10, and the clock of the conversion code is supplied to an input terminal 9. Outputs QE-QH are supplied to a pattern checking circuit 4 to receive patten checking. If these outputs correspond to none of bit patterns and synchronize with the common clock CK2, a check signal (d) is delivered.
JP10869880A 1980-08-06 1980-08-06 Coding and decoding system of binary data Granted JPS5733414A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10869880A JPS5733414A (en) 1980-08-06 1980-08-06 Coding and decoding system of binary data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10869880A JPS5733414A (en) 1980-08-06 1980-08-06 Coding and decoding system of binary data

Publications (2)

Publication Number Publication Date
JPS5733414A true JPS5733414A (en) 1982-02-23
JPS634268B2 JPS634268B2 (en) 1988-01-28

Family

ID=14491361

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10869880A Granted JPS5733414A (en) 1980-08-06 1980-08-06 Coding and decoding system of binary data

Country Status (1)

Country Link
JP (1) JPS5733414A (en)

Also Published As

Publication number Publication date
JPS634268B2 (en) 1988-01-28

Similar Documents

Publication Publication Date Title
US4337458A (en) Data encoding method and system employing two-thirds code rate with full word look-ahead
EP0304799A3 (en) Method and/or apparatus for demodulating a biphase signal
CA2019821A1 (en) Signal conversion circuit
EP0195989A3 (en) Method of demodulating an input signal phase-modulated by a binary bit sequence, and circuit arrangement therefor
JPS5733414A (en) Coding and decoding system of binary data
JPS5381222A (en) Digital signal transmitting system
JPS5750309A (en) Encoding and decoding system for binary data
JPS5468617A (en) Signal recorder-reproducer
DE3481963D1 (en) CIRCUIT FOR REGENERATION OF PERIODIC SIGNALS.
JPS52135220A (en) Information input system of electronic computer
JPS5725769A (en) Receiving system of facsimile picture information
JPS5799062A (en) Reception circuit for data transmission
JPS57132478A (en) Decoding system for variable length code
JPS6482821A (en) System and device for sequential decoding
JPS5595155A (en) Operation check system for counter
JPS6453632A (en) Data receiver
JPS5750310A (en) Encoding and decoding system for binary data
JPS5683163A (en) Encoding system
JPS56166527A (en) Time division time slot assigning system
JPS57154610A (en) Digital modulating and demodulating system
JPS57193868A (en) Recognizing system for mark discriminating circuit of optical mark reader
JPS57154611A (en) Digital modulating and demodulating system
JPS55140954A (en) Block error correcting device
JPS57111815A (en) Decoding system of binary code
JPS5726946A (en) Frame synchronizing system