JPS5734257A - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JPS5734257A
JPS5734257A JP10728780A JP10728780A JPS5734257A JP S5734257 A JPS5734257 A JP S5734257A JP 10728780 A JP10728780 A JP 10728780A JP 10728780 A JP10728780 A JP 10728780A JP S5734257 A JPS5734257 A JP S5734257A
Authority
JP
Japan
Prior art keywords
rom10
execution unit
external terminals
gate circuit
rom
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10728780A
Other languages
Japanese (ja)
Other versions
JPS6122820B2 (en
Inventor
Tomoji Nukiyama
Junichi Iwasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10728780A priority Critical patent/JPS5734257A/en
Publication of JPS5734257A publication Critical patent/JPS5734257A/en
Publication of JPS6122820B2 publication Critical patent/JPS6122820B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/226—Microinstruction function, e.g. input/output microinstruction; diagnostic microinstruction; microinstruction format

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To reduce the number of external terminals and to simplify the wiring by installing a gate circuit between an instruction decoder and an execution unit in an integrated circuit device containing the execution unit that executes by reading an ROM and programs of the ROM on the chip. CONSTITUTION:An ROM10 for program storing placed on the same chip and an instruction decoder 12 that decodes instruction codes read from said ROM10 and controls with timing a controlled signal as the result to output a microorder group 13 are provided. Further, processing determined on the basis of the order group 13 is executed in an execution unit 14 and a gate circuit 14 for switching the order group 13 to external terminals 17 is inserted between the circuits 12, 14. Hereby, as compared with a case where a conventional gate circuit is inserted between the ROM10 and the circuit R, the number of the external terminals 17 can be reduced, thereby allowing wiring to be simplified.
JP10728780A 1980-08-05 1980-08-05 Integrated circuit device Granted JPS5734257A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10728780A JPS5734257A (en) 1980-08-05 1980-08-05 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10728780A JPS5734257A (en) 1980-08-05 1980-08-05 Integrated circuit device

Publications (2)

Publication Number Publication Date
JPS5734257A true JPS5734257A (en) 1982-02-24
JPS6122820B2 JPS6122820B2 (en) 1986-06-03

Family

ID=14455259

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10728780A Granted JPS5734257A (en) 1980-08-05 1980-08-05 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5734257A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58219829A (en) * 1982-06-15 1983-12-21 Nec Corp Testing method of logical array

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58219829A (en) * 1982-06-15 1983-12-21 Nec Corp Testing method of logical array

Also Published As

Publication number Publication date
JPS6122820B2 (en) 1986-06-03

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