JPS5775367A - Microcomputer - Google Patents

Microcomputer

Info

Publication number
JPS5775367A
JPS5775367A JP55150947A JP15094780A JPS5775367A JP S5775367 A JPS5775367 A JP S5775367A JP 55150947 A JP55150947 A JP 55150947A JP 15094780 A JP15094780 A JP 15094780A JP S5775367 A JPS5775367 A JP S5775367A
Authority
JP
Japan
Prior art keywords
input
switch
output
cpu19
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55150947A
Other languages
Japanese (ja)
Inventor
Masahiro Mikami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP55150947A priority Critical patent/JPS5775367A/en
Publication of JPS5775367A publication Critical patent/JPS5775367A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)

Abstract

PURPOSE:To realize the conversion of a memory map of a system, by installing a converting switch, a circuit that applies temporarily the resetting to a CPU and a multiplexer that varies the input/output relation of an address decoder respectively. CONSTITUTION:A CPU19 is reset according to the state of a switch 30 and then started at the address 0000. For instance, when the output of a gate 31 is set at HIGH, a decoder 24 decodes the input 45. When the input 45 is 00, 10 and 11, outputs 49, 48, 47 and 46 are selectd respectively. Then an RAM27 and an ROM29 are selected when the switch 30 is in the state as shown in the diagram. When the switch 30 is set in the state opposite to that as shown in the diagram, the output of a gate 35 sets a latch 36. Then the CPU19 select only ROM28 and gives an access to it. In case the CPU19 jumps to a prescribed memory region and then resets a latch 36 by an input/output instruction, an access is given to the RAM27 and ROM28 respectively.
JP55150947A 1980-10-28 1980-10-28 Microcomputer Pending JPS5775367A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55150947A JPS5775367A (en) 1980-10-28 1980-10-28 Microcomputer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55150947A JPS5775367A (en) 1980-10-28 1980-10-28 Microcomputer

Publications (1)

Publication Number Publication Date
JPS5775367A true JPS5775367A (en) 1982-05-11

Family

ID=15507889

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55150947A Pending JPS5775367A (en) 1980-10-28 1980-10-28 Microcomputer

Country Status (1)

Country Link
JP (1) JPS5775367A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60209838A (en) * 1984-04-03 1985-10-22 Mitsubishi Electric Corp Program memory device
JP4727749B2 (en) * 2007-08-31 2011-07-20 パナソニック株式会社 Information processing device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60209838A (en) * 1984-04-03 1985-10-22 Mitsubishi Electric Corp Program memory device
JP4727749B2 (en) * 2007-08-31 2011-07-20 パナソニック株式会社 Information processing device

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