JPS5743419A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5743419A
JPS5743419A JP55119333A JP11933380A JPS5743419A JP S5743419 A JPS5743419 A JP S5743419A JP 55119333 A JP55119333 A JP 55119333A JP 11933380 A JP11933380 A JP 11933380A JP S5743419 A JPS5743419 A JP S5743419A
Authority
JP
Japan
Prior art keywords
layer
insulating layer
overall surface
manufacture
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55119333A
Other languages
Japanese (ja)
Inventor
Ichiro Fujita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55119333A priority Critical patent/JPS5743419A/en
Publication of JPS5743419A publication Critical patent/JPS5743419A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To remove burrs by physically etching the overall surface of an insulating layer and thereafter lifting it off in the lifting-off step in the case of forming the insulating layer to bury an electrode. CONSTITUTION:An insulating layer 3 of SiO2 is covered on the overall surface including an electrode layer 2 and a resist layer 4 formed on a silicon substrate 1. The overall surface is then etched by an ion beam emission, thereby removing burr B. Thereafter, the resist 4 and the insulating layer 3 are removed by a lift-off process, and a wiring layer 5 of second layer is then formed.
JP55119333A 1980-08-29 1980-08-29 Manufacture of semiconductor device Pending JPS5743419A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55119333A JPS5743419A (en) 1980-08-29 1980-08-29 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55119333A JPS5743419A (en) 1980-08-29 1980-08-29 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5743419A true JPS5743419A (en) 1982-03-11

Family

ID=14758877

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55119333A Pending JPS5743419A (en) 1980-08-29 1980-08-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5743419A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5443466A (en) * 1977-09-12 1979-04-06 Matsushita Electronics Corp Electrode formation method for semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5443466A (en) * 1977-09-12 1979-04-06 Matsushita Electronics Corp Electrode formation method for semiconductor device

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