JPS5753665A - Velocity signal converting circuit - Google Patents
Velocity signal converting circuitInfo
- Publication number
- JPS5753665A JPS5753665A JP12981180A JP12981180A JPS5753665A JP S5753665 A JPS5753665 A JP S5753665A JP 12981180 A JP12981180 A JP 12981180A JP 12981180 A JP12981180 A JP 12981180A JP S5753665 A JPS5753665 A JP S5753665A
- Authority
- JP
- Japan
- Prior art keywords
- counter
- signal
- value
- pulse
- multiplier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
- G01P3/00—Measuring linear or angular speed; Measuring differences of linear or angular speeds
- G01P3/42—Devices characterised by the use of electric or magnetic means
- G01P3/44—Devices characterised by the use of electric or magnetic means for measuring angular speed
- G01P3/48—Devices characterised by the use of electric or magnetic means for measuring angular speed by measuring frequency of generated current or voltage
- G01P3/481—Devices characterised by the use of electric or magnetic means for measuring angular speed by measuring frequency of generated current or voltage of pulse signals
- G01P3/489—Digital circuits therefor
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Linear Or Angular Velocity Measurement And Their Indicating Devices (AREA)
Abstract
PURPOSE:To convert a velocity signal into a digital or analog value, by using a frequency-to-digital converting circuit which has an arithmetic value at any time with a specified time constant by counting with an input signal. CONSTITUTION:An input pulse signal having a pulse rate H (Hpps) is differentiated by a differentiating circuit 11, whose output is sampled with input pulses Fpps from a timing generating circuit 14, and sampled values are supplied to a comparator 12. Its output is supplied to an up/down counter 13. When the pulse Fpps is inputted, on the other hand, a multiplier 15 generates a pulse proportional to the counted value of the counter 13 and supplies it to the comparator 12. As a result of this comparison, the value of the counter 13 is increased or decreased. Thus, the comparator 12, counter 13 and multiplier 15 forms a closed loop, so arithmetic is performed with a specified time constant. Therefore, a digital signal S4 is obtained from the counter 13, and an analog signal S3 from the multiplier 15.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12981180A JPS5753665A (en) | 1980-09-17 | 1980-09-17 | Velocity signal converting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12981180A JPS5753665A (en) | 1980-09-17 | 1980-09-17 | Velocity signal converting circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5753665A true JPS5753665A (en) | 1982-03-30 |
Family
ID=15018799
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12981180A Pending JPS5753665A (en) | 1980-09-17 | 1980-09-17 | Velocity signal converting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5753665A (en) |
-
1980
- 1980-09-17 JP JP12981180A patent/JPS5753665A/en active Pending
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