JPS5759352A - Manufacture of integrated circuit - Google Patents

Manufacture of integrated circuit

Info

Publication number
JPS5759352A
JPS5759352A JP55133798A JP13379880A JPS5759352A JP S5759352 A JPS5759352 A JP S5759352A JP 55133798 A JP55133798 A JP 55133798A JP 13379880 A JP13379880 A JP 13379880A JP S5759352 A JPS5759352 A JP S5759352A
Authority
JP
Japan
Prior art keywords
wiring
region
same potential
cells
cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55133798A
Other languages
Japanese (ja)
Inventor
Kenjiro Kawato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55133798A priority Critical patent/JPS5759352A/en
Publication of JPS5759352A publication Critical patent/JPS5759352A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To decrease the number of wiring patterns formed in a wiring region at the outside of a cell frame, to reduce the height of the wiring region and to curtail the area of a chip by wiring secions among cells by utilizing a dead region in the cells. CONSTITUTION:Same potential terminal positions are also defined in cell regions in addition to input/output terminal positions disposed on the sides of the conventional cell frame. When the same potential teminals 13-20, which are each defined at every plural number along the same potential patterns on the cells, are each connected mutually to each cell region 2, the wiring L16 and L17 connecting the same potential terminals arranged in different rows are defined in the wiring region 1, but wiring is each executed on the dead channels on the cell regions 2 about other wiring L13, L14, L15, L18, L19, L20. Accordingly, the channel number of the wiring patterns occupying the wiring region 1 is two, and the height hL' of the wiring region 1 an largely be reduced as compared to the conventional devices.
JP55133798A 1980-09-26 1980-09-26 Manufacture of integrated circuit Pending JPS5759352A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55133798A JPS5759352A (en) 1980-09-26 1980-09-26 Manufacture of integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55133798A JPS5759352A (en) 1980-09-26 1980-09-26 Manufacture of integrated circuit

Publications (1)

Publication Number Publication Date
JPS5759352A true JPS5759352A (en) 1982-04-09

Family

ID=15113265

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55133798A Pending JPS5759352A (en) 1980-09-26 1980-09-26 Manufacture of integrated circuit

Country Status (1)

Country Link
JP (1) JPS5759352A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60167444A (en) * 1984-02-10 1985-08-30 Hitachi Ltd High-density integrated circuit using building blocks
JPS61244046A (en) * 1985-04-22 1986-10-30 Nec Corp Arrangement method for peripheral block of standard cell
JPS639133A (en) * 1986-06-27 1988-01-14 エツセジ−エツセ　ミクロエレツトロニカ　ソチエタ　ペル　アノニマ Method of designing integrated microcomputer and integrated microcomputer with module construction obtained by the method
JPS63275140A (en) * 1987-04-30 1988-11-11 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン Integrated circuit device and manufacture of the same
JPS6417445A (en) * 1987-07-10 1989-01-20 Matsushita Electric Industrial Co Ltd Standard cell
JP2007279016A (en) * 2006-03-16 2007-10-25 Jfe Steel Kk Excitation and / or ionization method of substance, and analysis method and analysis apparatus using the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60167444A (en) * 1984-02-10 1985-08-30 Hitachi Ltd High-density integrated circuit using building blocks
JPS61244046A (en) * 1985-04-22 1986-10-30 Nec Corp Arrangement method for peripheral block of standard cell
JPS639133A (en) * 1986-06-27 1988-01-14 エツセジ−エツセ　ミクロエレツトロニカ　ソチエタ　ペル　アノニマ Method of designing integrated microcomputer and integrated microcomputer with module construction obtained by the method
JPS63275140A (en) * 1987-04-30 1988-11-11 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン Integrated circuit device and manufacture of the same
JPS6417445A (en) * 1987-07-10 1989-01-20 Matsushita Electric Industrial Co Ltd Standard cell
JP2007279016A (en) * 2006-03-16 2007-10-25 Jfe Steel Kk Excitation and / or ionization method of substance, and analysis method and analysis apparatus using the same

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