JPS6417445A - Standard cell - Google Patents

Standard cell

Info

Publication number
JPS6417445A
JPS6417445A JP62173220A JP17322087A JPS6417445A JP S6417445 A JPS6417445 A JP S6417445A JP 62173220 A JP62173220 A JP 62173220A JP 17322087 A JP17322087 A JP 17322087A JP S6417445 A JPS6417445 A JP S6417445A
Authority
JP
Japan
Prior art keywords
region
wiring
recessed
central part
cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62173220A
Other languages
Japanese (ja)
Other versions
JP2661916B2 (en
Inventor
Seiji Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62173220A priority Critical patent/JP2661916B2/en
Publication of JPS6417445A publication Critical patent/JPS6417445A/en
Application granted granted Critical
Publication of JP2661916B2 publication Critical patent/JP2661916B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To realize high integration, by disposing a power source line and an earth line horizontally on a central part and forming a recessed/projected region on a series of cells to make a wiring region small. CONSTITUTION:A power source line 2 is disposed horizontally in a constant width on a central part of a cell by the use of a metallic wiring on a first layer. An earth line 4 is also disposed horizontally in a constant width on the central part of the cell by the use of the metallic wiring on the first layer. Input lines 6, 8 are disposed vertically by the use of polycrystalline silicon. Thereupon, gate electrodes of all MOSFETs existing in a standard cell are disposed vertically. A recessed/projected region is thus formed on a series of cells. When one portion of a wiring region is assigned to the recessed/projected region, the wiring region can be made smaller than conventionally. Hence, high integration can be realized.
JP62173220A 1987-07-10 1987-07-10 Standard cell Expired - Lifetime JP2661916B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62173220A JP2661916B2 (en) 1987-07-10 1987-07-10 Standard cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62173220A JP2661916B2 (en) 1987-07-10 1987-07-10 Standard cell

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP7284896A Division JP2596406B2 (en) 1995-11-01 1995-11-01 Semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPS6417445A true JPS6417445A (en) 1989-01-20
JP2661916B2 JP2661916B2 (en) 1997-10-08

Family

ID=15956359

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62173220A Expired - Lifetime JP2661916B2 (en) 1987-07-10 1987-07-10 Standard cell

Country Status (1)

Country Link
JP (1) JP2661916B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0325951A (en) * 1989-06-23 1991-02-04 Nec Corp Layout cell of semiconductor integrated circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5759352A (en) * 1980-09-26 1982-04-09 Fujitsu Ltd Manufacture of integrated circuit
JPS5966146A (en) * 1982-10-08 1984-04-14 Toshiba Corp Semiconductor integrated circuit device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5759352A (en) * 1980-09-26 1982-04-09 Fujitsu Ltd Manufacture of integrated circuit
JPS5966146A (en) * 1982-10-08 1984-04-14 Toshiba Corp Semiconductor integrated circuit device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0325951A (en) * 1989-06-23 1991-02-04 Nec Corp Layout cell of semiconductor integrated circuit

Also Published As

Publication number Publication date
JP2661916B2 (en) 1997-10-08

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