JPS5761331A - Multioutput digital-to-analog converter - Google Patents
Multioutput digital-to-analog converterInfo
- Publication number
- JPS5761331A JPS5761331A JP13733480A JP13733480A JPS5761331A JP S5761331 A JPS5761331 A JP S5761331A JP 13733480 A JP13733480 A JP 13733480A JP 13733480 A JP13733480 A JP 13733480A JP S5761331 A JPS5761331 A JP S5761331A
- Authority
- JP
- Japan
- Prior art keywords
- data
- converter
- ram3
- analog
- digital
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/05—Digital input using the sampling of an analogue quantity at regular intervals of time, input from a/d converter or output to d/a converter
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
PURPOSE:To use only a digital-to-analog (D/A) converter, by storing plural digital data temporarily on an RAM, reading out in order and inputting them to D/A converter and storing the output of D/A converter in a holding capacitor. CONSTITUTION:Plural number of digital data are inputted to an RAM3 through a data bus 2 and are changed into writing operation through a changeover circuit 5 by a switching address bus 4 to store in the RAM3. The circuit 5 reads the data stored in the RAM3 by using a counter circuit 7 which is operated by an oscillator 6 in order and inputs them in the D/A converter 8. Then, the circuit converts the digital data into analog data and simultaneously when supplies them to the input of an analog multiplexer 10 by passing through a buffer amplifier 9, it selects the address of the analog multiplexer 10 which corresponds to the address of the RAM3. Then, analog data are converted and outputted in order and are stored in the holding capacitors 12-1-12-n. consequently, they are outputted from buffer amplifiers 13-1-13-n.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13733480A JPS5761331A (en) | 1980-09-30 | 1980-09-30 | Multioutput digital-to-analog converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13733480A JPS5761331A (en) | 1980-09-30 | 1980-09-30 | Multioutput digital-to-analog converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5761331A true JPS5761331A (en) | 1982-04-13 |
Family
ID=15196221
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13733480A Pending JPS5761331A (en) | 1980-09-30 | 1980-09-30 | Multioutput digital-to-analog converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5761331A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5962216A (en) * | 1982-09-30 | 1984-04-09 | M Syst Giken:Kk | Digital-analog converter |
-
1980
- 1980-09-30 JP JP13733480A patent/JPS5761331A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5962216A (en) * | 1982-09-30 | 1984-04-09 | M Syst Giken:Kk | Digital-analog converter |
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