JPS576480A - Buffer memory control system - Google Patents

Abstract

PURPOSE:To always execute a data processing at a high speed even when a main memory device in a low speed is used, by effectively using plural buffer memories. CONSTITUTION:In case when a block containing a necessary data does not exist in a buffer memory 22, a memory controlling circuit 21 requests its block to a memory controlling circuit 23. The circuit 23 which has received said request checks to ensure whether its high speed block exists in a buffer memory 24 or not, and transfers to the circuit 21 if it exists. If no high speed block exists, a block containing its high speed block is requested to a main memory device 25 in a low speed, and when it is transferred from the device 25, the requested high speed block is transferred to the memory controlling circuit 21. Other data of this block are stored in the memory 24. According to this constitution, as for the memory 22, that of a small capacity and a high speed is used, and on the other hand, as for the memory 24, one which is larger in capacity and lower in speed than the memory 22 is used. In this way, an information processing device having higher efficiency is realized by raising the probability of exist of a necessary data in each buffer memory.