JPH02280247A - Information processor - Google Patents

Abstract

PURPOSE:To execute an instruction word supply from a buffer storage to an instruction supplying means at a high speed by sending the instruction word of plural blocks from a main storage means when not even a single effective instruction word exists in the buffer storage. CONSTITUTION:An instruction supplying means 2 issues the read request of the instruction word to a buffer storage means 3 in order to supply the instruction word to an instruction processing means 1. The buffer storage means 3 investigates whether the required instruction word exists in the buffer storage or not, the instruction word is sent to the instruction supplying means 2 when is exists, and when it does not exist, the read request of the block to contain the instruction word to be required is issued to the main storage means. A control part 5 sends the instruction word of the block to be required from a storage part 4 to the buffer storage means 3 and, simultaneously, sends even the instruction word of plural blocks successive to the required block from the storage part 4 to the buffer storage means 3 when not a single effective instruction word exists in the buffer storage means 3. Thus, the instruction word supply can be made speedy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device having a main memory storing instruction words, and in particular, to an information processing device having a main memory means storing instruction words, and in particular, to an information processing device having a main memory means storing instruction words. The present invention relates to an information processing device that can speed up the supply of command words when the command is not available.

[Conventional technology]

In conventional information processing devices, when a buffer storage means requests the main storage means to read a block, the main storage means sends only the instruction word of the requested block to the buffer storage means. .

[Problem to be solved by the invention]

Therefore, in the conventional information processing device described above, when there is no valid instruction word in the buffer memory,
Until valid commands are accumulated in the buffer memory, there is a low probability that the command requested by the command supply means will exist in the buffer memory, resulting in a delay in the supply of commands.

[Means for resolving the issue]

The information processing device of the present invention includes a main storage means for storing instruction words, an instruction processing means for decoding and processing the instruction words, and an information processing device located between the main storage means and the instruction processing means, and storing information in the main storage means. an instruction supplying means for reading out the instruction word that is being processed and supplying it to the instruction processing means; and a part of the instruction word stored in the main storage means, which is located between the main storage means and the instruction supplying means buffer storage means for storing copies in blocks, the main storage means comprising:
It is characterized by comprising a control circuit for sending the instruction words of a plurality of blocks consecutive to the block as well as the instruction words of the block to the buffer storage means when there is a request to read a block from the buffer storage means. shall be.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The instruction supply means 2 issues an instruction word read request to the buffer storage means 3 in order to supply the instruction word to the instruction processing means 1. The buffer storage means 3 checks whether the requested instruction word exists in the buffer storage, and if so, sends the instruction word to the instruction supply means 2. If it does not exist, a read request for the block containing the requested instruction word is issued to the main storage means.

The control unit 5 stores the command word of the requested block in the storage unit 4.
When there is no valid command word in the buffer storage means 3, the command words of a plurality of blocks consecutive to the requested block are also sent from the storage section 4 to the buffer storage means 3. .

〔Effect of the invention〕

As explained above, the present invention buffers a large number of instructions with one instruction request by sending multiple blocks of instructions from the main memory when there is no valid instruction in the buffer memory. Since the instructions can be stored in the memory, the instruction words can be supplied from the buffer memory to the instruction supply means at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention. 1... Instruction processing means, 2... Instruction supplying means, 3...
- Buffer storage means, 4... Storage section, 5... Control section, 6
...Main memory means.

Claims (1)

[Claims] a main storage means for storing instruction words, an instruction processing means for decoding and processing the instruction words, and reading out the instruction words stored in the main storage means between the main storage means and the instruction processing means; an instruction supply means for supplying the instruction to the instruction processing means; and a buffer that is located between the main storage means and the instruction supply means and stores a copy of a part of the instruction word stored in the main storage means in units of blocks. storage means, when the main storage means receives a request to read a block from the buffer storage means, the main storage means sends the command words of the block as well as the command words of a plurality of blocks consecutive to the block to the buffer storage means. An information processing device comprising a control circuit for.