JPS5771029A - Data device - Google Patents

Data device

Info

Publication number
JPS5771029A
JPS5771029A JP55147116A JP14711680A JPS5771029A JP S5771029 A JPS5771029 A JP S5771029A JP 55147116 A JP55147116 A JP 55147116A JP 14711680 A JP14711680 A JP 14711680A JP S5771029 A JPS5771029 A JP S5771029A
Authority
JP
Japan
Prior art keywords
error
interface information
holding
circuit
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55147116A
Other languages
Japanese (ja)
Inventor
Kenji Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55147116A priority Critical patent/JPS5771029A/en
Publication of JPS5771029A publication Critical patent/JPS5771029A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE:To facilitate the bracketing of a fault when an error is detected and to decrease holding circuits, by using holding circuits in common in a data processor which performs logical operation processing according to transferred interface information. CONSTITUTION:If an error is detected in interface information, the interface information is switched by a selecting circuit 20 to be applied to a holding circuit 24, and another interface information determined by a priority switching control signal generating circuit 25 is transferred to an external device to discriminate, on the basis of the information and error signals from parity checking circuits 11-13, whether the error is caused by the external device side or a main device side. Further, the holding circuit 24 is used in common, so the holding circuits are decreased in number.
JP55147116A 1980-10-20 1980-10-20 Data device Pending JPS5771029A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55147116A JPS5771029A (en) 1980-10-20 1980-10-20 Data device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55147116A JPS5771029A (en) 1980-10-20 1980-10-20 Data device

Publications (1)

Publication Number Publication Date
JPS5771029A true JPS5771029A (en) 1982-05-01

Family

ID=15422884

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55147116A Pending JPS5771029A (en) 1980-10-20 1980-10-20 Data device

Country Status (1)

Country Link
JP (1) JPS5771029A (en)

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