JPS5771159A - Heterogeneous electroplating method for circuit substrate - Google Patents
Heterogeneous electroplating method for circuit substrateInfo
- Publication number
- JPS5771159A JPS5771159A JP55146301A JP14630180A JPS5771159A JP S5771159 A JPS5771159 A JP S5771159A JP 55146301 A JP55146301 A JP 55146301A JP 14630180 A JP14630180 A JP 14630180A JP S5771159 A JPS5771159 A JP S5771159A
- Authority
- JP
- Japan
- Prior art keywords
- copper foil
- device hole
- region
- circuit substrate
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/40—Leadframes
- H10W70/453—Leadframes comprising flexible metallic tapes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/04—Manufacture or treatment of leadframes
Landscapes
- Manufacturing Of Printed Wiring (AREA)
- Wire Bonding (AREA)
Abstract
PURPOSE:To reduce number of processes and to improve reliability by a method wherein a film resistive against plating solution is laminated on a back surface of a flexible circuit substrate, a device hole is sealed at one side and filled with a plating resist, and a finger region of a copper foil is protected. CONSTITUTION:A copper foil 1 is laminated with an intermediary of an adhesive layer 2 on a base film 3 having a device hole 4 disposed, and by forming a finger 1a having a bonding region 1c on the copper foil 1 of the device hole, a circuit substrate is completed. A lining film 6 consisting of a film such as Luminar or the like is laminated on the back of the substrate, for example a screen printing is performed on the figer region, a plating resist 5 is filled into the device hole 4, and after applying protection on the finger, gold plating is applied on a necessary region of the copper foil 1. In this constitution by possible reduction of processes for screen printing necessary for formation of mask layers to be used for different kind of plating, a fault rate can be reduced.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55146301A JPS5771159A (en) | 1980-10-21 | 1980-10-21 | Heterogeneous electroplating method for circuit substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55146301A JPS5771159A (en) | 1980-10-21 | 1980-10-21 | Heterogeneous electroplating method for circuit substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5771159A true JPS5771159A (en) | 1982-05-01 |
| JPS6252947B2 JPS6252947B2 (en) | 1987-11-07 |
Family
ID=15404578
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55146301A Granted JPS5771159A (en) | 1980-10-21 | 1980-10-21 | Heterogeneous electroplating method for circuit substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5771159A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63500837A (en) * | 1985-08-08 | 1988-03-24 | マツクダ−ミツド インコ−ポレ−テツド | Printed circuit board manufacturing method |
-
1980
- 1980-10-21 JP JP55146301A patent/JPS5771159A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63500837A (en) * | 1985-08-08 | 1988-03-24 | マツクダ−ミツド インコ−ポレ−テツド | Printed circuit board manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6252947B2 (en) | 1987-11-07 |
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