JPS5772321A - Manufacture of seiconductor device - Google Patents

Manufacture of seiconductor device

Info

Publication number
JPS5772321A
JPS5772321A JP55148939A JP14893980A JPS5772321A JP S5772321 A JPS5772321 A JP S5772321A JP 55148939 A JP55148939 A JP 55148939A JP 14893980 A JP14893980 A JP 14893980A JP S5772321 A JPS5772321 A JP S5772321A
Authority
JP
Japan
Prior art keywords
mask
substrate
insulation film
etching
insulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55148939A
Other languages
Japanese (ja)
Inventor
Iwao Higashinakagaha
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55148939A priority Critical patent/JPS5772321A/en
Publication of JPS5772321A publication Critical patent/JPS5772321A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs

Landscapes

  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To lead out an electrode wiring from a diffusion layer of small area securely without considering a discrepancy of a mask by a method wherein a connection hole is formed in an insulation film by anisotropic dry etching. CONSTITUTION:A portion of the first insulation film 12 formed on a semiconductor substrate 11 is removed and a diffusion layer 13 of an impurity is formed by using the film 12 as a mask. Then the second insulation film 14 is formed overall the surface. Then the overall surface of this substrate 11 is etched by anisotropic dry etching such as reactive ion etching by which the substrate is exposed in plasma in Freon gas between parallel-pole electrodes. With above method etching is progressed only in a vertical direction and a connection hole 15 is formed leaving the thin second insulation layer 14 inside the 1st insulation layer 12 which is used as the mask. Then on electrode wiring 16 such as of aluminum is formed by a conventional method.
JP55148939A 1980-10-24 1980-10-24 Manufacture of seiconductor device Pending JPS5772321A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55148939A JPS5772321A (en) 1980-10-24 1980-10-24 Manufacture of seiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55148939A JPS5772321A (en) 1980-10-24 1980-10-24 Manufacture of seiconductor device

Publications (1)

Publication Number Publication Date
JPS5772321A true JPS5772321A (en) 1982-05-06

Family

ID=15464033

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55148939A Pending JPS5772321A (en) 1980-10-24 1980-10-24 Manufacture of seiconductor device

Country Status (1)

Country Link
JP (1) JPS5772321A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5966170A (en) * 1982-10-08 1984-04-14 Toshiba Corp Manufacture of semiconductor device
JPS59155128A (en) * 1983-02-23 1984-09-04 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS59181614A (en) * 1983-03-31 1984-10-16 Toshiba Corp Manufacture of semiconductor device
JPS605514A (en) * 1983-06-24 1985-01-12 Toshiba Corp Manufacture of semiconductor device
JPS6028272A (en) * 1983-07-27 1985-02-13 Toshiba Corp Semiconductor device
JPS62500134A (en) * 1984-08-30 1987-01-16 アメリカン テレフオン アンド テレグラフ カムパニ− Electrical contacts in semiconductor devices
US4707457A (en) * 1986-04-03 1987-11-17 Advanced Micro Devices, Inc. Method for making improved contact for integrated circuit structure
JPH033324A (en) * 1989-05-13 1991-01-09 Hyundai Electron Ind Co Ltd Manufacture of semiconductor connector
US5663097A (en) * 1991-06-21 1997-09-02 Canon Kabushiki Kaisha Method of fabricating a semiconductor device having an insulating side wall

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5966170A (en) * 1982-10-08 1984-04-14 Toshiba Corp Manufacture of semiconductor device
JPS59155128A (en) * 1983-02-23 1984-09-04 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS59181614A (en) * 1983-03-31 1984-10-16 Toshiba Corp Manufacture of semiconductor device
JPS605514A (en) * 1983-06-24 1985-01-12 Toshiba Corp Manufacture of semiconductor device
JPS6028272A (en) * 1983-07-27 1985-02-13 Toshiba Corp Semiconductor device
JPS62500134A (en) * 1984-08-30 1987-01-16 アメリカン テレフオン アンド テレグラフ カムパニ− Electrical contacts in semiconductor devices
US4641420A (en) * 1984-08-30 1987-02-10 At&T Bell Laboratories Metalization process for headless contact using deposited smoothing material
US4707457A (en) * 1986-04-03 1987-11-17 Advanced Micro Devices, Inc. Method for making improved contact for integrated circuit structure
JPH033324A (en) * 1989-05-13 1991-01-09 Hyundai Electron Ind Co Ltd Manufacture of semiconductor connector
US5663097A (en) * 1991-06-21 1997-09-02 Canon Kabushiki Kaisha Method of fabricating a semiconductor device having an insulating side wall

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