JPS5773591A - Fixed delay inserting removing memory circuit - Google Patents

Fixed delay inserting removing memory circuit

Info

Publication number
JPS5773591A
JPS5773591A JP55148999A JP14899980A JPS5773591A JP S5773591 A JPS5773591 A JP S5773591A JP 55148999 A JP55148999 A JP 55148999A JP 14899980 A JP14899980 A JP 14899980A JP S5773591 A JPS5773591 A JP S5773591A
Authority
JP
Japan
Prior art keywords
flop
flip
phase comparison
width
fixed delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55148999A
Other languages
Japanese (ja)
Inventor
Yuzo Fujii
Toshio Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55148999A priority Critical patent/JPS5773591A/en
Publication of JPS5773591A publication Critical patent/JPS5773591A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

PURPOSE:To prevent data signals from disturbance due to the generation of insertion/removal of delay after passing a stated period by inserting/removing a fixed delay required at intial status to fix the entitled circuit on a stable side. CONSTITUTION:If an initial status such as electric power supply is generated, an initial status detector 7 operates to set up a set/reset flip-flop 9. As the result, Q and Q outputs from the flip-flop 9 are set to ''1'' and ''0'' respectively, pulses S2, R2 are selected by selectors 11, 12 and a phase comparison width EP is set up to a prescribed value. An AND gate 14 finds ''and'' between the phase comparison width PC and a write side standard pulse WFP and an alternate inverter 3 inverts to insert/remove delay and fix the circuit system to the stable side. At the same time, the flip-flop is reset and pulses S1, R1 are slected, so that the phase comparison width PC is set to normal width.
JP55148999A 1980-10-24 1980-10-24 Fixed delay inserting removing memory circuit Pending JPS5773591A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55148999A JPS5773591A (en) 1980-10-24 1980-10-24 Fixed delay inserting removing memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55148999A JPS5773591A (en) 1980-10-24 1980-10-24 Fixed delay inserting removing memory circuit

Publications (1)

Publication Number Publication Date
JPS5773591A true JPS5773591A (en) 1982-05-08

Family

ID=15465436

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55148999A Pending JPS5773591A (en) 1980-10-24 1980-10-24 Fixed delay inserting removing memory circuit

Country Status (1)

Country Link
JP (1) JPS5773591A (en)

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