JPS5773933A - Preparation of semiconductor device - Google Patents
Preparation of semiconductor deviceInfo
- Publication number
- JPS5773933A JPS5773933A JP55149898A JP14989880A JPS5773933A JP S5773933 A JPS5773933 A JP S5773933A JP 55149898 A JP55149898 A JP 55149898A JP 14989880 A JP14989880 A JP 14989880A JP S5773933 A JPS5773933 A JP S5773933A
- Authority
- JP
- Japan
- Prior art keywords
- mark
- electron
- psg21
- film
- aligning
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
- H10W46/501—Marks applied to devices, e.g. for alignment or identification for use before dicing
Landscapes
- Electron Beam Exposure (AREA)
Abstract
PURPOSE:To make clear the detection of a signal for a mark for positional alignment by electron beam scanning and to conduct thereby the positional alignment with high precision by removing the part of aligned position of an insulator film of a substrate before application of an electron-beam resist. CONSTITUTION:An opening 14 is made in SiO2 12 on a p-type Si substrate 11 and the mark 15 for aligning the position is made by etching. The film 12 being removed, a field oxidized film 16 and FET are provided by using the mark 15 by a conventional method and later are covered with PSG21. Then, a mask is prepared by applying an electron-beam resist PMMA 22a and conducting drawing and development thereon. By using this maks, the PSG21 is opened by plasma etching and subjected to high-temperature treatment in N2 and is thereby deformed. Then, a PMMA 22b is applied afresh, an electrode window is drawn and developed by using the mark 15 for aligning the position, the window is made in the PSG21 by the plasma etching, and an Al wiring 22 is attached thereto. Since the PSG in the part of the mark 15 for pigning the position is removed, the SN ratio of a position detection signal at the time of the electron-beam scanning is not deteriorated and there is no decline in the precision of overlapping of patterns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55149898A JPS5773933A (en) | 1980-10-25 | 1980-10-25 | Preparation of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55149898A JPS5773933A (en) | 1980-10-25 | 1980-10-25 | Preparation of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5773933A true JPS5773933A (en) | 1982-05-08 |
Family
ID=15485017
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55149898A Pending JPS5773933A (en) | 1980-10-25 | 1980-10-25 | Preparation of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5773933A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5132252A (en) * | 1988-04-28 | 1992-07-21 | Fujitsu Limited | Method for fabricating semiconductor devices that prevents pattern contamination |
-
1980
- 1980-10-25 JP JP55149898A patent/JPS5773933A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5132252A (en) * | 1988-04-28 | 1992-07-21 | Fujitsu Limited | Method for fabricating semiconductor devices that prevents pattern contamination |
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