JPS5775047A - Timing extracting circuit - Google Patents

Timing extracting circuit

Info

Publication number
JPS5775047A
JPS5775047A JP55151683A JP15168380A JPS5775047A JP S5775047 A JPS5775047 A JP S5775047A JP 55151683 A JP55151683 A JP 55151683A JP 15168380 A JP15168380 A JP 15168380A JP S5775047 A JPS5775047 A JP S5775047A
Authority
JP
Japan
Prior art keywords
circuit
pulses
inputted
signal
extracting circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55151683A
Other languages
Japanese (ja)
Inventor
Yusuke Kamitsuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP55151683A priority Critical patent/JPS5775047A/en
Publication of JPS5775047A publication Critical patent/JPS5775047A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0066—Detection of the synchronisation error by features other than the received signal transition detection of error based on transmission code rule

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To reduce the number of parts and make troublesome adjustments unnecessary, by constituting a circuit only by a differentiating circuit, a delay circuit, and an OR circuit. CONSTITUTION:An input signal (a) (binary AMI signal) is inputted to a logical differentiating circuit 1, and pulses (b) synchronized with the rise and the fall are extracted. Pulses (b) are inputted to not only an OR circuit 9 directly but also a delay circuit 8. Pulses (c) delayed in the delay circuit 8 by a constant time are inputted to the OR circuit 9 also. The OR signal between pulses (b) and (c) is outputted from the OR circuit 9 and becomes a timing signal (d).
JP55151683A 1980-10-29 1980-10-29 Timing extracting circuit Pending JPS5775047A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55151683A JPS5775047A (en) 1980-10-29 1980-10-29 Timing extracting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55151683A JPS5775047A (en) 1980-10-29 1980-10-29 Timing extracting circuit

Publications (1)

Publication Number Publication Date
JPS5775047A true JPS5775047A (en) 1982-05-11

Family

ID=15523965

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55151683A Pending JPS5775047A (en) 1980-10-29 1980-10-29 Timing extracting circuit

Country Status (1)

Country Link
JP (1) JPS5775047A (en)

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