JPS577628A - Pulse frequency modulator - Google Patents

Abstract

PURPOSE:To miniaturize a pulse frequency modulator (PFM) and to reduce its power consumption, by adding a resistor and a capacitor to a D type master slave flip-flop circuit (DMS-FF). CONSTITUTION:When the initial potential of a capacitor 31 is high, an H-level signal is inputted to a CML7 to input its output to a CML8, and then the output of the CML8 goes to a level H, thereby inputting an H-level signal to the C1 of a DMS-FF39. At this time, an H-level signal is outputted from a terminal Q1 to charge a capacitor 33 (to Vc3) via a resistance 34, holding a terminal S1 at the level H. On the other hand, an L-level signal is inputted to a terminal R1 via an inverter 37 and a delay circut 13. When the terminal S1 is at the level H, a terminal Q1' is also at the level H. As the terminal Q1' goes to the level H, the transistor 5 of a CML9 turns on to discharge the capacitor 31 to a potential where oscillation is stable.