JPS5776842A - Pattern forming method - Google Patents

Pattern forming method

Info

Publication number
JPS5776842A
JPS5776842A JP55153103A JP15310380A JPS5776842A JP S5776842 A JPS5776842 A JP S5776842A JP 55153103 A JP55153103 A JP 55153103A JP 15310380 A JP15310380 A JP 15310380A JP S5776842 A JPS5776842 A JP S5776842A
Authority
JP
Japan
Prior art keywords
mask
substrate
pattern
back side
sputtering
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55153103A
Other languages
Japanese (ja)
Inventor
Yoshio Koshikawa
Masahiro Miyazaki
Yushi Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55153103A priority Critical patent/JPS5776842A/en
Publication of JPS5776842A publication Critical patent/JPS5776842A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/50—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for positioning, orientation or alignment
    • H10P72/57—Mask-wafer alignment
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
    • H05K3/143—Masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits

Landscapes

  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To remove a pattern deposited on a substrate under the back side of a mask by performing sputtering under the state the mask is placed on the substrate, and performing sputter etching on the entire surface of the substrate whereon said mask is mounted. CONSTITUTION:The mask 2 having an opening 3 is placed over the substrate 1, and the sputtering is performed. Since thereis a fine between the substrate 1 and the mask 2, atoms which have come to the back side of the mask and deposited on the substrate 1, forms a pattern 5 whose width is broader than that of opening area A. After the sputtering process, the mask is removed, the sputter etching is performed, and the thin pattern part under the back side of the mask is removed. In this way, highly accurate pattern is obtained without a special process.
JP55153103A 1980-10-31 1980-10-31 Pattern forming method Pending JPS5776842A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55153103A JPS5776842A (en) 1980-10-31 1980-10-31 Pattern forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55153103A JPS5776842A (en) 1980-10-31 1980-10-31 Pattern forming method

Publications (1)

Publication Number Publication Date
JPS5776842A true JPS5776842A (en) 1982-05-14

Family

ID=15555032

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55153103A Pending JPS5776842A (en) 1980-10-31 1980-10-31 Pattern forming method

Country Status (1)

Country Link
JP (1) JPS5776842A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8557044B2 (en) 2006-10-17 2013-10-15 Samsung Electronics Co., Ltd. Shadow mask, method of manufacturing the same and method of forming thin film using the same
WO2016134329A1 (en) * 2015-02-20 2016-08-25 Si-Ware Systems Selective step coverage for micro-fabricated structures

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8557044B2 (en) 2006-10-17 2013-10-15 Samsung Electronics Co., Ltd. Shadow mask, method of manufacturing the same and method of forming thin film using the same
WO2016134329A1 (en) * 2015-02-20 2016-08-25 Si-Ware Systems Selective step coverage for micro-fabricated structures
CN107250033A (en) * 2015-02-20 2017-10-13 斯维尔系统 The selective stepcoverage of micro Process structure
JP2018508375A (en) * 2015-02-20 2018-03-29 シーウェア システムズＳｉ−Ｗａｒｅ Ｓｙｓｔｅｍｓ Selective step coverage for microfabricated structures
US10562055B2 (en) 2015-02-20 2020-02-18 Si-Ware Systems Selective step coverage for micro-fabricated structures
CN107250033B (en) * 2015-02-20 2020-10-09 斯维尔系统 Selective step coverage of microfabricated structures
US11499218B2 (en) 2015-02-20 2022-11-15 Si-Ware Systems Selective step coverage for micro-fabricated structures

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