JPS5776856A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5776856A
JPS5776856A JP55152669A JP15266980A JPS5776856A JP S5776856 A JPS5776856 A JP S5776856A JP 55152669 A JP55152669 A JP 55152669A JP 15266980 A JP15266980 A JP 15266980A JP S5776856 A JPS5776856 A JP S5776856A
Authority
JP
Japan
Prior art keywords
film
si3n4
layer
oxide film
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55152669A
Other languages
English (en)
Inventor
Hiroshi Nozawa
Hisahiro Matsukawa
Junichi Matsunaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55152669A priority Critical patent/JPS5776856A/ja
Publication of JPS5776856A publication Critical patent/JPS5776856A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01Manufacture or treatment
    • H10W10/061Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/181Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
JP55152669A 1980-10-30 1980-10-30 Manufacture of semiconductor device Pending JPS5776856A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55152669A JPS5776856A (en) 1980-10-30 1980-10-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55152669A JPS5776856A (en) 1980-10-30 1980-10-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5776856A true JPS5776856A (en) 1982-05-14

Family

ID=15545502

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55152669A Pending JPS5776856A (en) 1980-10-30 1980-10-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5776856A (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58194382A (ja) * 1982-05-08 1983-11-12 Matsushita Electric Ind Co Ltd 発光装置用電極構体
US4818235A (en) * 1987-02-10 1989-04-04 Industry Technology Research Institute Isolation structures for integrated circuits
US5002898A (en) * 1989-10-19 1991-03-26 At&T Bell Laboratories Integrated-circuit device isolation
US5338750A (en) * 1992-11-27 1994-08-16 Industrial Technology Research Institute Fabrication method to produce pit-free polysilicon buffer local oxidation isolation
US5432113A (en) * 1992-08-04 1995-07-11 Nippon Steel Corporation Method of making a semiconductor memory device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58194382A (ja) * 1982-05-08 1983-11-12 Matsushita Electric Ind Co Ltd 発光装置用電極構体
US4818235A (en) * 1987-02-10 1989-04-04 Industry Technology Research Institute Isolation structures for integrated circuits
US5002898A (en) * 1989-10-19 1991-03-26 At&T Bell Laboratories Integrated-circuit device isolation
JPH03145730A (ja) * 1989-10-19 1991-06-20 American Teleph & Telegr Co <Att> 集積回路半導体デバイスの製造方法
US5432113A (en) * 1992-08-04 1995-07-11 Nippon Steel Corporation Method of making a semiconductor memory device
US5338750A (en) * 1992-11-27 1994-08-16 Industrial Technology Research Institute Fabrication method to produce pit-free polysilicon buffer local oxidation isolation

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