JPS5776860A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPS5776860A
JPS5776860A JP15232680A JP15232680A JPS5776860A JP S5776860 A JPS5776860 A JP S5776860A JP 15232680 A JP15232680 A JP 15232680A JP 15232680 A JP15232680 A JP 15232680A JP S5776860 A JPS5776860 A JP S5776860A
Authority
JP
Japan
Prior art keywords
mesa groove
mesa
glass
region
junction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15232680A
Other languages
Japanese (ja)
Inventor
Masafumi Miyagawa
Tomohito Ono
Yoshihisa Furuya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Components Co Ltd
Original Assignee
Toshiba Corp
Toshiba Components Co Ltd
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Components Co Ltd, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15232680A priority Critical patent/JPS5776860A/en
Priority to DE3143216A priority patent/DE3143216C2/en
Publication of JPS5776860A publication Critical patent/JPS5776860A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching

Landscapes

  • Dicing (AREA)
  • Thyristors (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE: To prevent the generation of a glass crack, etc. by forming a convex section to a streak bottom shaped in a cutting prearranged region of a semiconductor wafer with a P-N junction.
CONSTITUTION: When a mesa groove 412 is formed in the cutting prearranged region of the semiconductor wafer with the P-N junction through mesa etching, the convex section 414 is shaped to the bottom of the mesa groove 412 because the rate of etching differs according to the difference of impurity concentration between an N type silicon wafer 401 and an N+ type impurity region. A glass layer 416 is formed to the mesa groove 412, and the mesa groove 412 is cut by means of a diamond scriber. Accordingly, the generation of the glass crack, chipping, etc. due to the dependency of the thickness of the glass film can be prevented.
COPYRIGHT: (C)1982,JPO&Japio
JP15232680A 1980-10-31 1980-10-31 Semiconductor device and its manufacture Pending JPS5776860A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP15232680A JPS5776860A (en) 1980-10-31 1980-10-31 Semiconductor device and its manufacture
DE3143216A DE3143216C2 (en) 1980-10-31 1981-10-30 Semiconductor wafer with dicing sections and process for their manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15232680A JPS5776860A (en) 1980-10-31 1980-10-31 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPS5776860A true JPS5776860A (en) 1982-05-14

Family

ID=15538076

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15232680A Pending JPS5776860A (en) 1980-10-31 1980-10-31 Semiconductor device and its manufacture

Country Status (2)

Country Link
JP (1) JPS5776860A (en)
DE (1) DE3143216C2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001009932A1 (en) * 1999-07-30 2001-02-08 Nippon Sheet Glass Co., Ltd. Method of dicing semiconductor wafer into chips, and structure of groove formed in dicing area

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0750700B2 (en) * 1989-06-27 1995-05-31 三菱電機株式会社 Semiconductor chip manufacturing method
JP2890380B2 (en) * 1991-11-27 1999-05-10 三菱電機株式会社 Semiconductor device and manufacturing method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IE33405B1 (en) * 1968-12-09 1974-06-12 Gen Electric Semiconductor wafers sub-dividable into pellets and methods of fabricating same
DE2306842C3 (en) * 1973-02-12 1981-10-29 Siemens AG, 1000 Berlin und 8000 München Process for producing a plurality of semiconductor elements from a single semiconductor wafer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001009932A1 (en) * 1999-07-30 2001-02-08 Nippon Sheet Glass Co., Ltd. Method of dicing semiconductor wafer into chips, and structure of groove formed in dicing area
US6300224B1 (en) 1999-07-30 2001-10-09 Nippon Sheet Glass Co., Ltd. Methods of dicing semiconductor wafer into chips, and structure of groove formed in dicing area

Also Published As

Publication number Publication date
DE3143216A1 (en) 1982-06-03
DE3143216C2 (en) 1985-10-31

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