JPS5776864A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5776864A
JPS5776864A JP55153136A JP15313680A JPS5776864A JP S5776864 A JPS5776864 A JP S5776864A JP 55153136 A JP55153136 A JP 55153136A JP 15313680 A JP15313680 A JP 15313680A JP S5776864 A JPS5776864 A JP S5776864A
Authority
JP
Japan
Prior art keywords
layer
wiring layer
wiring
contact
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55153136A
Other languages
Japanese (ja)
Inventor
Toru Inaba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55153136A priority Critical patent/JPS5776864A/en
Publication of JPS5776864A publication Critical patent/JPS5776864A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To improve the degree of integration of an integrated circuit by forming a trapezoid polysilicon layer, the surface thereof is oxidized, under the first wiring layer of section where the first wiring layer and the second wiring layer separated by a layer insulating layer contact. CONSTITUTION:When the first wiring layers 1, 11 are shaped onto a lower layer insulating layer 4 formed onto a semiconductor substrate not shown and the second wiring layer 21 and a cover glass layer 24 are molded through an upper layer phosphours-silicon-glass layer 14, the trapezoid polysilicon layer 6, the surface thereof has an oxide film 6', is formed under the section where the first wiring layer 1 and the second wiring layer 21 contact. Accordingly, the second wiring layer can be shaped positively even when the positions of through-holes for contact are displaced, and the degree of integration is also improved because the contact forming section need not be magnified and molded.
JP55153136A 1980-10-31 1980-10-31 Manufacture of semiconductor device Pending JPS5776864A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55153136A JPS5776864A (en) 1980-10-31 1980-10-31 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55153136A JPS5776864A (en) 1980-10-31 1980-10-31 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5776864A true JPS5776864A (en) 1982-05-14

Family

ID=15555783

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55153136A Pending JPS5776864A (en) 1980-10-31 1980-10-31 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5776864A (en)

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