JPS5779721A - Automatic gain controlling circuit - Google Patents

Automatic gain controlling circuit

Info

Publication number
JPS5779721A
JPS5779721A JP15515680A JP15515680A JPS5779721A JP S5779721 A JPS5779721 A JP S5779721A JP 15515680 A JP15515680 A JP 15515680A JP 15515680 A JP15515680 A JP 15515680A JP S5779721 A JPS5779721 A JP S5779721A
Authority
JP
Japan
Prior art keywords
agc
signal
input signal
adsta
inputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15515680A
Other languages
Japanese (ja)
Inventor
Fusakichi Ogawara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP15515680A priority Critical patent/JPS5779721A/en
Publication of JPS5779721A publication Critical patent/JPS5779721A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control

Landscapes

  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To achieve stable AGC operation even if the time interval for AGC is longer, by detecting an average level of an AGC input signal and processing it digitally for AGC. CONSTITUTION:When the time for AGC reset comes, an ADSTA signal is outputted, an analog gate G turns off, an AGC input signal is rectified at a diode D and flows to a capacitor C, and a potential at point A increases. On the other hand, the ADSTA signal is delayed at a delay circuit DL and inputted to an analog-digital conversion circuit A/D, and the output of an amplifier IC is A/D-converted. The output data from an A/D conversion circuit is latched at a latch circuit L directly, and an attenuator ATT is driven with the inversion of the latch signal, the AGC input signal is converted to a prescribed level and inputted to the system, and an analog gate turns on at the time point.
JP15515680A 1980-11-06 1980-11-06 Automatic gain controlling circuit Pending JPS5779721A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15515680A JPS5779721A (en) 1980-11-06 1980-11-06 Automatic gain controlling circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15515680A JPS5779721A (en) 1980-11-06 1980-11-06 Automatic gain controlling circuit

Publications (1)

Publication Number Publication Date
JPS5779721A true JPS5779721A (en) 1982-05-19

Family

ID=15599749

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15515680A Pending JPS5779721A (en) 1980-11-06 1980-11-06 Automatic gain controlling circuit

Country Status (1)

Country Link
JP (1) JPS5779721A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5532216A (en) * 1978-08-23 1980-03-06 Matsushita Electric Ind Co Ltd Automatic recording level setter
JPS5562510A (en) * 1978-11-02 1980-05-12 Itsuki Ban Electronic volume and automatic sound recording level setting unit using it

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5532216A (en) * 1978-08-23 1980-03-06 Matsushita Electric Ind Co Ltd Automatic recording level setter
JPS5562510A (en) * 1978-11-02 1980-05-12 Itsuki Ban Electronic volume and automatic sound recording level setting unit using it

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