JPS5779738A - Delay equalizing circuit - Google Patents

Abstract

PURPOSE:To reduce the capacity of delay memory and to minimize the delayed amount of data, by discriminating input data with most delay out of several input data, detecting the difference of delay among this input data and each input data and performing readout control of each data written in the delay memory accroding to the difference of delay, in a delay equalizing circuit used for parallel transmission data. CONSTITUTION:In response to the clock from a terminal 1 by a write-in address counter 4, an address to write in input data from terminals 2a...2c to delay memories 5a...5c is produce. Write-in address storage circuits 10a-10c store the write-in address in response to the output of frame synchronizing circuits 3a-3c. The address corresponds to the delay in the input data. When a discrimination circuit 11 detects the frame synchronizing pulse of input data with most delay out of input data, an address corresponding to the delay of input data is loaded to readout address counters 9a-9c and the data are read out from each delay memory according to each readout address counter.