JPS5444445A - Memory control unit - Google Patents
Memory control unitInfo
- Publication number
- JPS5444445A JPS5444445A JP11071677A JP11071677A JPS5444445A JP S5444445 A JPS5444445 A JP S5444445A JP 11071677 A JP11071677 A JP 11071677A JP 11071677 A JP11071677 A JP 11071677A JP S5444445 A JPS5444445 A JP S5444445A
- Authority
- JP
- Japan
- Prior art keywords
- memories
- write
- clock signal
- memory
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
Landscapes
- Memory System (AREA)
Abstract
PURPOSE:To enable to write in and read out in high speed, by using low speed memories, through the split processing of memory write-in and readout. CONSTITUTION:When the write-in mode in designated with the control circuit 8, the input signal fed to the terminal 13 is alternately and respectively memorized in FF6, 7 for data memory with the clock signals 11 and 12 frequency-divided 5 into 1/2. That is the time memorized in FF6, 7 is twice the period of the clock signal 10. Further, the location of either of memories 1, 2 memorizing the content of FF6, 7 is determined with the address counters 3 and 4, and since the counters 3 and 4 are operated in synchronizing with FF6, 7, the input signal is stored split in the memories 1, 2 in the speed of clock signal. That is, in this case, the clock signal can be taken twice the processing ability of memory. Further, similarly, in the case of readout, the output of memories 1, 2 can be gated and alternately read out with the output selection circuit 9 by the output signal 11 of FF5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11071677A JPS5444445A (en) | 1977-09-14 | 1977-09-14 | Memory control unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11071677A JPS5444445A (en) | 1977-09-14 | 1977-09-14 | Memory control unit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5444445A true JPS5444445A (en) | 1979-04-07 |
Family
ID=14542658
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11071677A Pending JPS5444445A (en) | 1977-09-14 | 1977-09-14 | Memory control unit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5444445A (en) |
-
1977
- 1977-09-14 JP JP11071677A patent/JPS5444445A/en active Pending
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