JPS5791560A - Semiconductor non-volatile memory - Google Patents

Semiconductor non-volatile memory

Info

Publication number
JPS5791560A
JPS5791560A JP55167481A JP16748180A JPS5791560A JP S5791560 A JPS5791560 A JP S5791560A JP 55167481 A JP55167481 A JP 55167481A JP 16748180 A JP16748180 A JP 16748180A JP S5791560 A JPS5791560 A JP S5791560A
Authority
JP
Japan
Prior art keywords
drain
gate
diffused region
voltage
writing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55167481A
Other languages
Japanese (ja)
Inventor
Shinpei Tsuchiya
Takashi Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55167481A priority Critical patent/JPS5791560A/en
Publication of JPS5791560A publication Critical patent/JPS5791560A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H10D30/683—Floating-gate IGFETs having only two programming levels programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling

Landscapes

  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To lower erasing and writing voltages by reducing the superposed part of a floating gate and a drain diffused region via a gate insulating film smaller than the drain diffusion depth to form a tunnel injection region by lateral diffusion. CONSTITUTION:A voltage between the voltage applied between a drain diffused region 14 and a floating gate 15 and a drain voltage becomes lower in case of writing when the capacity between the gate 15 and the drain 14 is small. Accordingly, the superposed part between the gate and the drain diffused region is formed lower than the drain diffusion depth, and the gate insulating film is reduced partly in the vicinity of the drain diffused region. Thus, the erasing/ writing voltage can be largely lowered.
JP55167481A 1980-11-28 1980-11-28 Semiconductor non-volatile memory Pending JPS5791560A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55167481A JPS5791560A (en) 1980-11-28 1980-11-28 Semiconductor non-volatile memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55167481A JPS5791560A (en) 1980-11-28 1980-11-28 Semiconductor non-volatile memory

Publications (1)

Publication Number Publication Date
JPS5791560A true JPS5791560A (en) 1982-06-07

Family

ID=15850474

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55167481A Pending JPS5791560A (en) 1980-11-28 1980-11-28 Semiconductor non-volatile memory

Country Status (1)

Country Link
JP (1) JPS5791560A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6329969A (en) * 1986-07-23 1988-02-08 Nec Corp Manufacturing method of floating gate type non-volatile semiconductor memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6329969A (en) * 1986-07-23 1988-02-08 Nec Corp Manufacturing method of floating gate type non-volatile semiconductor memory device

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