JPS58101320A - Double address controlling system - Google Patents
Double address controlling systemInfo
- Publication number
- JPS58101320A JPS58101320A JP19984881A JP19984881A JPS58101320A JP S58101320 A JPS58101320 A JP S58101320A JP 19984881 A JP19984881 A JP 19984881A JP 19984881 A JP19984881 A JP 19984881A JP S58101320 A JPS58101320 A JP S58101320A
- Authority
- JP
- Japan
- Prior art keywords
- address
- terminal
- signal
- output signal
- decoder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000009977 dual effect Effects 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 abstract description 3
- 238000006243 chemical reaction Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- 210000000554 iris Anatomy 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 241000711443 Bovine coronavirus Species 0.000 description 1
- 101000710137 Homo sapiens Recoverin Proteins 0.000 description 1
- 102100034572 Recoverin Human genes 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、１個のアドレスデコーダを有する受信ｉ１ｔ
、複数個のアドレスデー−〆を有する受信器と同機に動
作畜せる２重アドレス制御方式ＫＩｌするもので参る。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a receiver ilt with one address decoder.
The dual address control system KIl allows the receiver to operate simultaneously with a receiver having a plurality of address data limits.
第１図に示すように、中央制御装置ＣＣからアドレス信
号を送出して複数の受信器ＲＣＶ１〜ＲＣＶ％のうちの
１つを指定し、スイッチＳＷ１〜ＳＷ％のうちの１つの
オン、オフ等の制御を行なうシステムに於いて紘、受信
＠ＲＣＶｊ〜ＢＣＶｓにそれぞれ割轟てられたアドレス
対応の構成の１個のアドレスレコーダが設けられている
。従ってアドレスデ；−ダについてみると、アドレス信
号によ）指定基れ大もののみが出力動作することになる
から、利用率が低いことになる。As shown in FIG. 1, an address signal is sent from the central controller CC to designate one of the plurality of receivers RCV1 to RCV%, and one of the switches SW1 to SW% is turned on or off, etc. In the control system, one address recorder configured to correspond to the addresses assigned to each of the reception @RCVj to BCVs is provided. Therefore, when looking at the address data, only the data designated by the address signal (according to the address signal) will output, resulting in a low utilization rate.
又アドレス信号のみでスイッチ勢を指定し、且つオン、
オフ等の状態制御上行なうシステムＫｍいては、例えば
各スイッチに＠幽てられたオン制御用のアドレス信号と
オフ制御用の７ドレス信号とを用いることになル、その
為に受信器Ｋａ２個のアドレスデ；−ダを設けなければ
ならないことになる。Also, specify the switch force using only the address signal, and turn on and off.
In a system Km that performs state control such as off, for example, an address signal for on control and a 7 address signal for off control, which are sent to each switch, are used, and for this purpose two receivers Ka are used. This means that an address reader must be provided.
本発明は％ １個のアドレスデー−ダに簡単な構成を追
加して、恰も複数個のアドレスデコーダを備えているよ
うに、複数のアドレス信号のデコードを可能とすること
を目的とすｈ４のである。以下実施例にりいて詳細に説
明する。The purpose of the present invention is to add a simple configuration to a single address datader so that it can decode multiple address signals as if it were equipped with multiple address decoders. be. This will be explained in detail below with reference to Examples.
絡２ｗＪは本発明の実施例の要部ブロック線図であシ、
１はアドレスデコーダで、端子１１１１１ｃアドレス信
号・が入力され、端子１１〜Ａ４に外部からアドレス設
定が可能であって、入力アドレス信号・の直列並列変換
を行なうシフトレジスタと、設定アドレスと並列に変換
され九人カアドレス信号との一致比較を行なうゲート回
路とを含み、集積回路化されているものである。２Ｆｉ
フリＶプ７ａＶプで、そのクロνり端子Ｃにアドレスデ
；−ダ１の出力信号＆が加えられる。又５，６は抵抗、
４はコンデンサ、５はダイオードであｐｌこれら紘クリ
ップ７０ツブ２のイニシャルセット回路を構成している
。Connection 2wJ is a block diagram of the main part of the embodiment of the present invention,
1 is an address decoder to which a terminal 11111c address signal is input, an address can be set from the outside to terminals 11 to A4, and a shift register is used to perform serial-to-parallel conversion of the input address signal and convert it in parallel with the set address. It includes a gate circuit for performing a match comparison with the address signal of nine people, and is an integrated circuit. 2Fi
The output signal & of the address register 1 is applied to the reverse terminal C of the flip voltage 7aV. Also, 5 and 6 are resistances,
4 is a capacitor, and 5 is a diode, which constitutes an initial set circuit for these clips 70 and 2.
この実施例は４ビツト構成のアドレス信号を用い危場合
についてのものであシ、アドレスデコーダ１の端子Ａｌ
〜Ａｓｔｉｃそれぞれ＃１１１． ＃Ｑ＃、 １ｌｊｌ
ｌ ｌ設定し、端子Ａ４にはクリップフｍｙプ２の端子
盃の出力信号−會加え、設定アドレスの最下位ビットを
“０′と“ぜとに切換える場食を示している。This embodiment uses a 4-bit address signal and is for emergency situations.
~Astic #111 each. #Q#, 1ljl
11 is set, the output signal of the terminal cup of the clip amplifier 2 is added to the terminal A4, and the lowest bit of the setting address is switched between "0" and "both".
又７リツプフＩ２ｖプ２の端子ｉの出力信号−はデータ
端子りに加えられ、セット端子ＪＫａ前述のイニシャル
セット回路によ〕セット信号が加えられ、リセット端子
Ｒは接地されている。入力アドレス信号８に対応した出
力信号は１、アドレスデコーダ１の出力信号−［−ＯＵ
Ｔ １として用いるか、又は７リツプフロツプ２の端子
Ｑの出力信号ｆ：０ＵＴ２として用いることができるも
のである。Further, the output signal - of the terminal i of the 7-lip amplifier I2v is applied to the data terminal, a set signal is applied to the set terminal JKa by the above-mentioned initial set circuit, and the reset terminal R is grounded. The output signal corresponding to the input address signal 8 is 1, and the output signal of address decoder 1 is -[-OU
It can be used as T1 or as the output signal f:0UT2 of the terminal Q of the 7-lip-flop 2.
第５図は動作説明図でＴｏｊ＋、りは入力アドレス信号
・、（−）はアドレスデコーダ１の出力信号ｂ１（ｓ）
は７リツプ７０ツブ２の端子りの出力信号−の−例會示
す。イニシャルセラ） Ｋ ！ ｎ ７１７シプ７０ツ
ブ２がセットされると、アドレスデコーダ１の端子１４
には０”が加えられるので、設定アドレスは１０１Ｇ’
″となる。アドレス信号６１〜８４が“１０１０”であ
ると、アドレスデコーダ１の出力信号すが“１°とな）
、この出力信号すの立上りで７リツプ７０シブ２は反転
動作し、端子りの出力信号−は“１′となる。従ってア
ドレスデコーダ１の設定アドレス紘“１０１ぜとなる。Figure 5 is a diagram explaining the operation, where Toj+ is the input address signal, and (-) is the output signal b1(s) of the address decoder 1.
7 shows an example of the output signal at the terminal of 70 tube 2. Initial Sera) K! When n 717 ship 70 knob 2 is set, terminal 14 of address decoder 1
Since 0" is added to , the setting address is 101G'
If the address signals 61 to 84 are "1010", the output signal of the address decoder 1 will be "1°".
At the rising edge of this output signal, the 7-lip 70 shift 2 performs an inverted operation, and the output signal at the terminal becomes "1".Therefore, the set address of the address decoder 1 becomes "101".
次にアドレス信号蟲１〜・４が“１０１１″となると、
アドレスデコーダ１の出力信号すは豊び“１”とな〕、
その立上）でツリツブフロツブ２＃′ｉ反転動作し、端
子ｉの出力信号−は“０１となる。従りてアドレスデコ
ーダ１の設定アドレスは最初と同じ“１０１Ｇ”となる
。Next, when address signals 1 to 4 become “1011”,
The output signal of address decoder 1 becomes "1"],
At its rising edge), the block 2#'i inverts and the output signal at the terminal i becomes "01".Therefore, the set address of the address decoder 1 becomes "101G", which is the same as at the beginning.
前述の如くアドレス信号６１〜−４を“１０１０“とす
ると、ツリツブ７０ツブ２の端子Ｑは′０”となル、そ
れによりて例えばスイッチをオン制御すると、次のアド
レス信号−１〜・４が“１０１１”のと自、フリップ７
Ｅ１ｙプ２の端子Ｑｔ！″１“となるから、スイッチの
オフ制御を行なわせることがで龜る。As mentioned above, when the address signals 61 to -4 are set to "1010", the terminal Q of the block 70 and block 2 becomes '0', so that, for example, when a switch is turned on, the next address signals -1 to -4 are set to "1010". is “1011” and flip 7
Terminal Qt of E1ypu2! Since it becomes "1", it becomes difficult to perform switch-off control.
即ち１個のアドレスデコーダ１によル、２つの′アドレ
ス信号のデコードを行なうことができることになる。又
フリップ７０シブ２の端子ｉの出力信号−をアドレスデ
コーダ１の端子１１〜Ａ４の任意の１端子又抹複数端子
に加える構成とするζ゛とも可能である。又フリップフ
ロｙ７’１頁に追加して縦ｆ接続し、それぞれの７リツ
プ７キツプの出力端子とアドレスデコーダ１のアドレス
設定用の端子と！ＩＩ！すれに、１個のアドレスデ−／
１ｔ［数のアドレス信号のデコード用として動作させる
ことができる。That is, one address decoder 1 can decode two address signals. It is also possible to have a configuration in which the output signal - of the terminal i of the flip 70 SIB 2 is applied to any one or more terminals of the terminals 11 to A4 of the address decoder 1. Also, add it to the flip-flop y7'1 page and connect it vertically to the output terminals of each 7 lip and 7 kip and the address setting terminal of address decoder 1! II! One address date/
It can be operated for decoding address signals of 1t [number.
以上説明し比ように、本発明は、１個のアドレスデコー
ダを少なくとも２つのアドレス信号のデコード用として
動作させることができるもので、アドレスデコーダの利
用率を向上して経済的な構成とすることができ、各種の
制御システムに適用することができる。As described above, the present invention enables one address decoder to operate for decoding at least two address signals, and provides an economical configuration by improving the utilization rate of the address decoder. It can be applied to various control systems.
菖１ｉｇＦｉ制御システムの一例の概略ブロック−図ｂ
Ｊｇ Ｒ図線本発明の実施例の一１Ｉ部ブロック銀図
、菖５ｉｌｌ紘動作１！羽図でめゐ。
１はアドレスデー−ダ、２は７リツプ７０ツブ、５．６
は抵抗、４はコンデンサ、５紘ダイオード、ＳＩＢアド
レス値号の入力端子、１１〜Ａ４はアドレス設定用の端
子でめゐ。
特許出願人 富士通電装株式金社
代場人弁塩士玉蟲久五部
外５名Schematic block diagram of an example of an irises 1igFi control system - Figure b
Jg R diagram line 11I part block silver diagram of the embodiment of the present invention, irises 5ill Hiro movement 1! Hazu de mei. 1 is address data, 2 is 7 lip 70 lip, 5.6
is a resistor, 4 is a capacitor, 5 is a diode, SIB address value input terminal, and 11 to A4 are address setting terminals. Patent applicant: Fujitsu Denso Co., Ltd. Kinsha Daibajin Bentenshi Tamamukyu 5 people
Claims (1)
ス信号と設定アドレスとの一致比較を行なうアドレスデ
ー−ダと、腋アドレスデ；−ダの出力信号により反転動
作するクリップ７０ジグと會備え、峡７すシグフ謬ジグ
の出力信号ｔｌＨｅ７ドレスデ；−ダのアドレス設定用
の端子に加え、複数の入力アドレス信号のデコードを前
記アドレスデコーダによシ行なわせることｔ−特徴とす
る２重アドレス制御方式。It is equipped with an address datater that has a terminal for setting an address from the outside and compares the input address signal with a set address, and a clip 70 jig that operates in reverse according to the output signal of the armpit address datader. 7. A dual address control system characterized in that the address decoder decodes a plurality of input address signals in addition to a terminal for setting the address of the output signal tlHe7 address decoder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19984881A JPS58101320A (en) | 1981-12-11 | 1981-12-11 | Double address controlling system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19984881A JPS58101320A (en) | 1981-12-11 | 1981-12-11 | Double address controlling system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58101320A true JPS58101320A (en) | 1983-06-16 |
| JPH0337219B2 JPH0337219B2 (en) | 1991-06-04 |
Family
ID=16414649
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19984881A Granted JPS58101320A (en) | 1981-12-11 | 1981-12-11 | Double address controlling system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58101320A (en) |
-
1981
- 1981-12-11 JP JP19984881A patent/JPS58101320A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0337219B2 (en) | 1991-06-04 |
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