JPS58103671A - パタ−ンチエツカ−の制御方法 - Google Patents

パタ−ンチエツカ−の制御方法

Info

Publication number
JPS58103671A
JPS58103671A JP56202106A JP20210681A JPS58103671A JP S58103671 A JPS58103671 A JP S58103671A JP 56202106 A JP56202106 A JP 56202106A JP 20210681 A JP20210681 A JP 20210681A JP S58103671 A JPS58103671 A JP S58103671A
Authority
JP
Japan
Prior art keywords
pattern
checking
checker
test
adaptor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56202106A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0129266B2 (2
Inventor
Akio Sano
佐野 昭夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56202106A priority Critical patent/JPS58103671A/ja
Publication of JPS58103671A publication Critical patent/JPS58103671A/ja
Publication of JPH0129266B2 publication Critical patent/JPH0129266B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
JP56202106A 1981-12-15 1981-12-15 パタ−ンチエツカ−の制御方法 Granted JPS58103671A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56202106A JPS58103671A (ja) 1981-12-15 1981-12-15 パタ−ンチエツカ−の制御方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56202106A JPS58103671A (ja) 1981-12-15 1981-12-15 パタ−ンチエツカ−の制御方法

Publications (2)

Publication Number Publication Date
JPS58103671A true JPS58103671A (ja) 1983-06-20
JPH0129266B2 JPH0129266B2 (2) 1989-06-08

Family

ID=16452058

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56202106A Granted JPS58103671A (ja) 1981-12-15 1981-12-15 パタ−ンチエツカ−の制御方法

Country Status (1)

Country Link
JP (1) JPS58103671A (2)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61259597A (ja) * 1985-05-13 1986-11-17 株式会社日立製作所 プリント基板の配線方法
JP2007147474A (ja) * 2005-11-29 2007-06-14 Micronics Japan Co Ltd センサ基板並びにこれを用いる検査方法及び装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61259597A (ja) * 1985-05-13 1986-11-17 株式会社日立製作所 プリント基板の配線方法
JP2007147474A (ja) * 2005-11-29 2007-06-14 Micronics Japan Co Ltd センサ基板並びにこれを用いる検査方法及び装置

Also Published As

Publication number Publication date
JPH0129266B2 (2) 1989-06-08

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