JPS58106928A - Decoding for interframe code - Google Patents

Abstract

PURPOSE:To prevent the enlargement of picture degradation in reproducing, by switching a one-line memory and a zero level transmitting circuit by the occurrence of a code error of a transmission line. CONSTITUTION:If a code error occurs on a digital transmission 1 line 10 and a synchronizing code SYNC is not detected by a synchronizing code detecting circuit 16, the switching operation of a switching circuit 15 is performed to switch the circuit 15 to the side of a zero level transmitting circuit 14. The zero level is transmitted to the output of a interframe code decoder 17 and is outputted as an analog signal from an output terminal 21. Thereafter, when the code error is recovered to detect the synchronizing code SYNC, the switching operation of the switching circuit 15 is performed, and the circuit 15 is operated so that an output (d) of a one-line memory 13 is inputted to the decoder 17.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a decoding method in Frey Gokan coding method 2, in which the decoded signal is delayed and the code 1MI is added to the decoded signal.
A decoding method is adopted that reproduces an image from decoded data only when n is absent.

Conventionally, in the inter-frame prediction side coding method, as a method of reducing the degraded image due to the transmission path code 611! which is input from the transmission path when #A is detected. l There is a method of reproducing the image signal of the previous frame as the image signal of the tenth frame, assuming that there is no error at all. This is because image signals have a large frame correlation, so even if one feature of the previous frame is reproduced in the current frame, there is little deterioration.

However, in this method, the decoding of the scanning line in which the code 1 @ shi occurred is replaced with the image code of the previous frame from the next scanning line in which the code error occurred, and the decoding of the scanning line in which the code 1 @ shi occurred is performed using differential PCM (DPCM
) etc., the deterioration caused by multiple code errors is magnified. In particular, when the color component of the input 111i signal is multiplexed with the luminance signal in the time domain, color deterioration is noticeable.

SUMMARY OF THE INVENTION An object of the present invention is to provide a 7-ray, 1-Goseki code O decoding system that does not reproduce the enlarged nine-image deterioration caused by such a transmission path error kK.

This will be explained in detail below using the drawings.

FIG. 1 shows an embodiment of the invention, in which 1 is a signal input terminal;
2 is a frame/Dffi converter, 3Fi subtracter, 4 is an intraframe encoder, 5 is an adder, 6 is a frame memory, 7 is a multiplexer for multiplexing encoded data and synchronization code 5YNC, 8 is a buffer memory, 9 is an encoded signal output terminal, 10
1 is a digital transmission line, 11 is an encoded signal input terminal, 12 is a backup memory, 13 is a 1-line memory, 14 is a zero level sending circuit, 15 is a switching circuit, 16 is a synchronization code detection circuit, and 17 is within the 7th frame. Decoder, 18 is adder, 19#'i
.

A frame memory, 20 a D/A converter, and 21 a signal output terminal.

A good signal input from the 10 input terminal is digitized by the A/D converter 2, and is converted into a frame memo IJ (FMS) by the subtracter 3.
) 6 is taken. The difference output is encoded by an intra-frame encoder (COD) 4 such as DPCM, and the encoded signal is split into two, one being sent to a multiplexer (MOX) 7 and the other being added to a Fi frame integrator. The signal is supplied to the frame memory 6, is added to the output of the frame memory 6, and is input to the frame memory 6. The multiplexer 7 multiplexes the input signal so that it outputs the output signal of the intraframe encoding circuit 4 in the encoding period, and outputs the synchronization signal code 5YNC in the synchronization signal period, and outputs the interframe code -
It is input to the buffer memory (BFS) 8 as a 4a signal. The backup memory 8 is read out at a constant speed and sent to the digital transmission trace 0 from the terminal 9.

The interframe code image signal received through the transmission line 10 and the terminal 11 is stored in a buffer memory (BFR) 12. The backup memory 12 is read out, one input is input to the synchronization code detection circuit (DFT) 1s to verify whether a correct synchronization code is received in the synchronization signal period, and the other input is input to the first line memo (IHMKM) 13. Ru. 1
A good signal stored in the line memory 13 is switched to a switching circuit (5W)
15 is input. In the switching circuit 15, when the synchronization code is detected by the synchronization code detection circuit 16, the one line memory 13
When the synchronization code cannot be detected, the output signal of the zero level sending circuit 14 is sent to an intraframe decoder (DEC) 17.
Output to. The intra-frame decoder 17 decodes the intra-frame code, and the adder 18 decodes the frame memory (FM
R) is added to the output of 19, and the frame-related code is decoded. Adder 180 Addition result Frame memory 19
The decoded output signal is input to the output terminal 21 via the D/MU converter 2o and supplied as a decoded output signal.

When a code error occurs in the digital transmission path 10 and the synchronization code detection circuit 16 does not detect the synchronization code 8YNC, the switching circuit 15 is caused to perform a switching operation to switch to the zero level sending circuit 14. This zero level is transmitted to the output of intra-frame decoding @17, and the output of frame memory 19 becomes zero.
In addition to the output of the adder 18, the KD/mu converter 20 outputs an analog signal from the output terminal 21. After that, the code error is recovered, and when the synchronization code detection circuit 16 detects the synchronization code 8YNC, the switching circuit 15 performs the switching operation and 1-) The output of the in-memory 13 becomes the input to the intra-frame decoder 17. It works like this.

Next, an example of the operation of this system will be explained using the waveform diagram of each part in Figure #12. 1 is the output waveform of the adder 18 of the previous frame, and is also the output waveform of the frame memory 19 of the current frame, and b is the input waveform of the 12-in memory 13. C indicates the detection time of the synchronization code detection circuit 16 with "↑", d indicates the l line memo January 30 output waveform, * indicates the output waveform of the synchronization code detection circuit 16 indicating the presence or absence of a synchronization code, f indicates the output waveform of the switching circuit 15, g indicates the output waveform of the intraframe decoder 17, and h indicates the output waveform of the adder 18 of the current frame. .

That is, when the synchronization code 5YNC is not detected, the output of the 1-line memory 13 is ignored by the switching circuit 15, and the switching circuit 15
The output of becomes fO. Therefore, the abnormal code caused by the code mb that occurred at time T is not input into the intraframe decoding@17, and the extremely large image quality deterioration caused by the decoding # and riK is not output from the output terminal 21. It is also possible to configure a 7-frame relational encoding system in which the encoder 4 is omitted, and in this case, the intraframe decoder 17 on the receiver side is also omitted.

As explained above, according to the present invention, even if code ridges occur in the transmission path, the IO code is not used for reproduction at all by the 1-line memory, the zero level sending circuit, and the switching circuit,
Since the image before the frame is reproduced, there is very little deterioration in image quality. Therefore, in a teleconference (video conference), etc., by using a 1-line memory, a zero level sending circuit, and a switching circuit in the receiving section of the encoding device in a system that performs highly efficient transmission by 7-layer 15-level encoding. This means that image quality deterioration can be suppressed to a minimum.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of main parts of an embodiment of the present invention, and FIG. 2 is an enlarged explanatory diagram of the operation. 1, II: No. 11 input terminal, 2: A/D converter, 3:
Subtractor, 4: Intraframe encoder, 5, 18: Adder, 6
, 19: Frame memory, 7 Niga multiplexer, 8, 1
2: Buffer memory, 9.21: Signal output terminal, 10:
Digital transmission path, 13:1 line memory, 14: level sending circuit, 15: switching circuit, 16: synchronization code detection circuit, 17: intraframe decoder, 20: l)/A converter, a: 7 frame memory 19 output waveform, b=1 line memory 130 input waveform, C: synchronization code detection time, d: output waveform of 1 line memory 13, e: synchronization code detection circuit 16
f: output waveform of the switching circuit 15, g: output waveform of the intra-frame decoder 17, h: adder 1 of the current frame
This is an example of the output waveform of No. 8. Patent Applicant NEC Corporation Agent Taku Kusano Figure 1 O 2 Figure e 1 Amendment to Detection Procedure (
System) May 10, 1988 Commissioner of the Japan Patent Office 1, Indication of case Patent application No. 5,610,63782, Title of invention Decoding of interframe code 8, Relationship to case of person who makes m correction Patent applicant NEC Co., Ltd. Agent: 6615 Shinjuku 4-2-21 (Sumo Building), Shinjuku-ku, Tokyo Taku Kusano, Patent Attorney Date of amendment order: April 27, 1980 1. Subject of amendment: Column 7 of the name of the invention in the Wt document, amendment Contents (1) Middle Part 1 of the Specification, Name of Invention Column [Frame Procedure Sleeve Letter (Spontaneous) June 14, 1980 Director General of the Patent Office 1.8 Displays Patent Application 1982-2063782, Invention Name Decoding of interframe code 8, Relationship with the case of the person making the amendment Patent applicant NEC Corporation Tenshiki Rinto 4-2-21 Shinjuku, Shishijuku-ku, Tokyo
Sumo Building 5, subject of amendment Column 6 of title of invention in specification, content of amendment

Claims (1)

[Claims] (1) A one-line memory that stores a differentially encoded signal in an interframe code image signal such as a differentially encoded signal and a synchronization code for one horizontal scanning time, and a synchronization system that detects a synchronization code from the interframe coded image signal. It has a code detection circuit, a zero level sending (b) path, a switching circuit that switches the outputs of the 12-in memory and the zero level sending circuit, and a differential signal decoder that decodes the output signal of the switching circuit. , if the synchronization code is detected in the synchronization code detection circuit, the output of the one line memory is used as the output of the switching circuit, and if the synchronization code is not detected, the output of the zero level sending circuit is used as the output of the switching circuit. . A decoding method for interframe codes, characterized in that the difference signal decoder decodes the switching circuit output signal and reproduces an image.