JPS58112143A - Program controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] The present invention relates to a program control device for a computer.

In a Neumann type digital computer, there are cases where the operand is the contents of the memory at the 1) @ address following the address where the instruction code is stored. For example, #8t in Jin's memory
1. CP IF (CP IF)
tralNroceaalngUnit)rc When using the provided register It as St-data in this register I (hereinafter referred to as Registration I atrefvungt! call J, :), or using the contents of the register as address information. (hereinafter referred to as t-register indirect addressing).

However, in general, the time required to read and fill memory is
It takes longer than the time required to read and write a register, so the execution time of an instruction using immediate address referencing or direct addressing is longer than the execution time of an instruction using register addressing or register-related address referencing. become longer. This will be explained using the example shown in FIG. Now read the contents of memory,
AL U (4rithmetic lnd Log
Let's consider a process in which some calculation is performed on the ical unit ) and the result is stored in the accumulator. FIG. 1 (-) shows the case of internal reading of the memory using inter-register addressing. STAY) At 8-, the memory is accessed as the register contents t address.

In state 8-, the contents of the memory are stored in the MLUK, and the result is stored in the Achiemulator. On the other hand, 1. 1.: J1g1 Figure (b) shows the case where direct addressing is used to access the contents of a message. state 8
・A memory access is performed to retrieve address information from memory. In state 8m, address information is read from the memory, and the memory is accessed again at this address tI&. In states B and b, exactly the same operation as in state 8!1 described earlier is performed. In this way, when direct addressing is used, l-state takes more time than when register I indirect addressing is used, and the instruction execution speed decreases. Also, just because the addressing method is different, 85 extra states are required9, which means an increase in the number of words of the so-called control memory in the control unit. Additionally, in order to prevent the number of words from increasing, the addressing process part is stored as a subroutine in control memory, and this subroutine is shared by different instruction codes. In order to fully realize this, hardware for subroutine processing is required.

The above explanation mainly takes the cases of direct addressing and register I indirect addressing as examples, but the same applies to the case of integer addressing and register addressing in terms of execution speed and number of memory words. I can say that. This is because even in the case of immediate addressing, execution of an instruction starts from a state where memory is being accessed. Therete V
t) Compared to the case of using a switch, an extra time is required for each state, resulting in an increase in instruction-line time. It also causes an increase in word $12) of control memory.

The purpose of the present invention is to eliminate the above-mentioned drawbacks of the conventional art. It is an object of the present invention to provide a GLODRAM control device capable of reducing the number of words to be decoded. The contents of the memory at the indicated address are temporarily stored in 1m order - some OV
A q register I group called ν registers, a q control unit that controls the program callan I and the Q register I group, and an instruction y that temporarily stores necessary ones of the outputs of the Qv registers as instruction codes. , a state register I indicating the instruction execution state, and the above,
The output of the instruction register, the output of the state counter, and the signal outputted from the Q control unit and indicating the state of the Q register group are input, and various overturning signals obtained by decoding or further encoding these are inputted to the The present invention is characterized by a control section that sequentially outputs and outputs data by fully incrementing a state counter.

An embodiment of the present invention will be described below based on the drawings. 1st
The figure shows one embodiment of the present invention, program memory (1)
is used to store instructions, program callan I
(2) provides an address signal (3) l to the program memory (1). i* Extracted program memory (1) O contents (6) are temporarily stored in q register (6). The number of open stars in the q register ill is l
Considering the case where 1@(1))K is equal to the maximum number of contents of the deroghumm memory (1) used in the state, this @ number becomes l. The contents (1) of the Q register c) are temporarily stored in the in-stock scene register (1), or are passed through the buffer 1 (8) to the pass (9).
) is output. The members of the Q control department are deroghumkaun! For (c), an increment signal 1111 that increases the counter content Yrl is output, and the Q register (61
gives a write signal (I21). This signal is output when the contents of the q register (5) are used and is used to write new data from the program memory (1) to the tct register (&). At this time, an increment signal 0 is also output, and the contents of the 10-gram counter (2) are incremented by 1.The program memory (1) is then accessed using this new address.

In other words, the q register (the contents of H are always updated to new data when used. Stay) counter O
``4 is reset when a new instruction code is stored in the inventory scene register (n), and is counted up sequentially after that, and the control unit t*ti installation scene register V register ( 7), inputs the state callan Ils and q status signal 94,
These are appropriately decoded or further encoded to output various control signals Hk at a high level. Q status signal 0@ is part of Q &1IJ (signal output from LO, Q
This indicates whether the contents of register (5) can be filled with unused contents. When the contents of Q register (5) are used,
The q control unit [phase] rc is sent a control signal 11 indicating this from the control unit I. Based on this control signal (I7), the QfllJ controller αQ controls the program counter (2) and the Q register (51111i-IJ) so that the Q register +51 is always filled with unused data.

Next, it will be explained that by using the circuit shown in FIG. 21, the state flow in FIG. 1 becomes the state flow in FIG. 5. As shown in Figure 1, state S1a when using register indirect addressing in Figure 1(b) and state 8- when using direct addressing in Figure 1(b) perform exactly the same operation. Therefore, so that these states can be shared in both addressing modes, instruction codes are assigned so that the Hamming distance is 1. Then, if the state ' can be shared, the bits that open when the Hamming distance is 1 are Leave it undecoded.As an example, the flow KfEj in Fig. 3 (-)
Instruction code t-(1010), , Figure S (b) (
Table 1 shows how the control unit #dish is decoded when the command code tube (1011) is set to D7a-. The state whose state counter is 1 can be shared, so
Bits 15 of the instruction code mentioned above are not decoded. Control unit/4rCfi, Q status signal indicating that the contents of Q register (51) are unused is also input, but this signal is not necessary when the contents of Q register (6) are not used. , so Figure S (
In the first state V and shared state M1 of register indirect addressing shown in Table 1, I
The IL status signal is decoded and then the case of direct addressing will be described. Conventionally, since it is necessary to first read the direct address from the memory when executing an instruction, a state θ, shown as vc in FIG. 1(b), is required. However, in the case of the present invention, when the instruction comes to the company, the direct address is already KQ register (5
), the state flow is as shown in Figure 3 (
We sincerely request that the direct address t-Q register (
We can start from state M, which outputs from b) through buffer (8) 1 to bus (9). However, since unused data does not always appear at the time of the Q register (51 contents), in the case of direct addressing, usj
As shown in state M in the Ax table, the Q status signal e~ is also targeted for decoding. Therefore, STI
If the output signal is O, no decode line of the control 5114IO is selected, all control signal lines are inactive, and the state signal line /Ql is not counted up.In this state, Qvt) When new data enters the bus Jl (!1), the q status signal ill becomes l and is decoded.
. When the state count field is counted up by the control signal -fc, the state transitions to ζ shown in the ls1 table.

Also, since the contents of Q and S) are used in state M and 1+, the control signal o
'Notify tain+tmsoo using *. Therefore, the q control part (a) sends a q register write signal (teatQ register +6), updates the contents of the Qv register (&), and sends a delogram kakunta (revc increment) mftillt to prepare the next state 1avc. As mentioned above, even in the case of direct addressing, as long as there is data in the q register (61), instructions can be executed at the same speed as in the case of register indirect addressing, !/. , states can be shared.

The above explanation is based on direct addressing and register XB.
I followed the case of k-address V-ng, but it is a good idea.8. r4-like V can also be said in the case of toad k 7 s+”7 f and di3. adrefsing.

To do this, first you need to access the menu.
In the case of SR addressing, this relationship is not necessary; this relationship f$ is the same as that between direct addressing and register indirect addressing, and the present invention can be applied thereto.

As explained above, according to the present invention, the forward speed t when addressing is performed using the contents of memory, and the execution speed t, q when addressing 1 is performed using registers.
They can be made equal under the assumption that the register contains data. Also, in a normal program, addressing is performed using the contents of memory in all states.
In the case of Oken, since the Q register rcFi data is stored, the execution speed of the entire program can be improved. Furthermore, for instructions that differ only in addressing method, by assigning their instruction codes so that the Hamming distance is 1, it is possible to share the state flow. In addition to being able to reduce the number of meco and negative wires in l, it is also possible to handle various addressing modes with a simple configuration. Ta.

tI! 1. Brief explanation 111 is a diagram showing an example of a state flow according to a conventional control method, and FIG. 2 is a diagram showing an example of a state flow according to the present invention! i! Figure S, a block diagram showing an example of a journey, is a diagram showing an example of a state flow according to the control method of the present invention.

('1)...Program memory, C2)...Program number I% (6)-Q register, Cη...Installation register, -Q control section, a--State counter , - 噌・-m* Part Figure 3 (a) 5-minute long dress 2

Claims (1)

[Claims] L: Consists of a memory for storing instructions, a program counter for giving a number signal to the memory, and several registers I for sequentially and temporarily storing the internal melodies of the homachi O and the message indicated by the program callan I. Qvsp Nu I group,
a q control unit that controls the program counter and the q register I group; The state callan I indicating the ib Reiryo row state, the output of the instrument register IO, the output of the state counter, and the signal output from the q control unit and indicating the Q&/JIFO state Wt are input, and these are input. The decoding unit further includes a control unit that encodes and outputs various control signals by incrementing the state counter t, and outputs the number of register SO stages t1 comprising the Q&/JI group 1*.
A grog-tum control device characterized in that fK is set equal to the maximum number of internal pieces of memory required for a dormitory row state, and the number of bits decoded by the control section is made fK.