JPS58112400A - Electronic circuit package erroneous insertion preventing mechanism by visual system - Google Patents

Electronic circuit package erroneous insertion preventing mechanism by visual system

Info

Publication number
JPS58112400A
JPS58112400A JP21527681A JP21527681A JPS58112400A JP S58112400 A JPS58112400 A JP S58112400A JP 21527681 A JP21527681 A JP 21527681A JP 21527681 A JP21527681 A JP 21527681A JP S58112400 A JPS58112400 A JP S58112400A
Authority
JP
Japan
Prior art keywords
electronic circuit
circuit package
package
erroneous insertion
visual system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21527681A
Other languages
Japanese (ja)
Inventor
渡辺 久雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP21527681A priority Critical patent/JPS58112400A/en
Publication of JPS58112400A publication Critical patent/JPS58112400A/en
Pending legal-status Critical Current

Links

Landscapes

  • Mounting Of Printed Circuit Boards And The Like (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (1)  発明の分野 本発明紘電子回路パッケージを電子回路パッケージシェ
ルフへ挿入する際の誤挿入防止機構に関し、特にこの誤
挿入防止を可視的に行なえる手段を設けた可視方式によ
る亀子囲路パッケージ誤挿入防止4l!榊に関する。
[Detailed Description of the Invention] (1) Field of the Invention The present invention relates to a mechanism for preventing erroneous insertion when an electronic circuit package is inserted into an electronic circuit package shelf, and in particular, a means for visually preventing this erroneous insertion is provided. 4L of prevention of incorrect insertion of Kameko enclosure package using visible method! Regarding Sakaki.

(2)従来技術と間組点 従来の電子FjiJ路パッケージ誤挿入防止機構は、第
1図に示すように裏面にバックボード3を備えた電子回
路パッケージシェルフ2の土部ま九下部に、列番号表示
ラベル2lまたは電子囲路パッケージ品名表示ラベル2
2勢を貼付し、電子囲路パッケージ1を電子回路パッケ
ージシェルフ2へ挿入する際に、電子囲路パッケージ1
上の電子回路パッケージ品名表示11と、これらの列番
号表示ラベル21または電子胞路パッケージ品名表示ラ
ベル22勢を保守者が比軟参照し、その一致、不一致を
チェックすることによシ、電子回路パッケージlの電子
回路パッケージシェルフ2における皺当位置又紘列以外
への誤挿入を防止していた。
(2) Conventional technology and assembly point As shown in FIG. Display label 2l or electronic enclosure package product name display label 2
When inserting the electronic circuit package 1 into the electronic circuit package shelf 2, the electronic circuit package 1
A maintenance person can refer to the above electronic circuit package product name display 11 and these column number display labels 21 or electronic circuit package product name display labels 22 and check whether they match or not. This prevents the package l from being erroneously inserted into a position other than the crease contact position or the horizontal row on the electronic circuit package shelf 2.

しかL7、このような従来の電子回路パッケージ−挿入
防止機構では、各表示ラベルの耽み違え勢のヒーーマン
・エラーによる電子回路パッケージの誤挿入に対して、
伺ら防ぐべき手段がないという欠点を有していた。
However, such a conventional electronic circuit package insertion prevention mechanism prevents incorrect insertion of the electronic circuit package due to the He-Man error caused by mistaking each display label.
The drawback was that there was no way to prevent it.

(3)発明の目的 本発明は、このような従来の欠点を改良した電子回路パ
ッケージ誤挿入防止機構を提供することにある。
(3) Object of the Invention The object of the present invention is to provide a mechanism for preventing erroneous insertion of an electronic circuit package, which improves the above-mentioned conventional drawbacks.

(4)発明の散点 本発明の電子−路バッケージー挿入防止機構れ、電子回
路パッケージの電子回路パッケージシェルフへの挿入に
際して、その挿入位t(列)の1糾をランプ番の可視表
示手段で表示することにより、電子回路パッケージの誤
挿入に対して防止を行なうものである。
(4) Discrepancies of the Invention The electronic circuit baggage insertion prevention mechanism of the present invention, when an electronic circuit package is inserted into the electronic circuit package shelf, detects one of the insertion positions t (column) using a visual display means of the lamp number. By displaying the information, it is possible to prevent incorrect insertion of the electronic circuit package.

(5)発明の実施例 第2図は本発明による電子回路パッケージ−挿入防止機
構の回路図、JlK3図は本発明による電子回路パッケ
ージ誤挿入防止機構の構造図である。これらの図に示す
電子回路パッケージ誤挿入防止機構は電子回路パッケー
ジ10の上部および下部に接触ランド10a¥rn個、
予備挿入位置マーク10bを、めらかじめ、共通マスク
パターンで作成し、電子回路バンク−710にi載され
た発光タイオードIOCと、電子回路パッケージ10の
上部および1;部の接触ランドl0JIとを、nmaの
電子回路パッケージに対応させて、ジャンパll1li
15により接続し、電子回路パッケージ1oの上部およ
び下部の振触ランド10mの位置的に見て対となってい
る1組を1樵として、n4m類の嫉絖パターンを汲定て
きる。
(5) Embodiments of the Invention FIG. 2 is a circuit diagram of a mechanism for preventing insertion of an electronic circuit package according to the present invention, and FIG. 3 is a structural diagram of a mechanism for preventing incorrect insertion of an electronic circuit package according to the present invention. The electronic circuit package misinsertion prevention mechanism shown in these figures includes contact lands 10a\rn on the upper and lower parts of the electronic circuit package 10,
The preliminary insertion position mark 10b is made smoothly and with a common mask pattern, and the light emitting diode IOC mounted on the electronic circuit bank 710 and the contact land 10JI on the top and part 1 of the electronic circuit package 10 are connected. , jumper ll1li to correspond to the nma electronic circuit package.
15, and a pair of vibrating lands 10m on the upper and lower parts of the electronic circuit package 1o are regarded as one woodcutter, and the n4m type wire pattern is determined.

次に、電子(ロ)路パッケージシェルフ20の上部およ
び下部の溝の部分の画情の、前述した電子回路パッケー
ジ10の上部および下部の接触ランドlO&と対応した
位置に接触バネ20aをセットすることによシ、電子回
路パッケージの場合とIWJ様に、n種類の位置に嶺触
バネ2゜aのセットパターンを仮定できる。
Next, set the contact springs 20a at positions corresponding to the contact lands lO& on the upper and lower parts of the electronic circuit package 10 described above in the image of the upper and lower grooves of the electronic circuit package shelf 20. Alternatively, in the case of electronic circuit packages and IWJ, it is possible to assume a set pattern of the ridge contact springs 2°a in n different positions.

このnmaのセットパターンは電子回路パッケージ20
と電子回路パッケージシェルフ30とをネジ35勢によ
り接続し、電源(+5V)30mおよび接地(E)30
bを電子回路パッケージシェルフ20の上部および下部
の接触バネ20aに供給する。
This nma set pattern is for electronic circuit package 20
and electronic circuit package shelf 30 with 35 screws, power supply (+5V) 30m and ground (E) 30m.
b to the upper and lower contact springs 20a of the electronic circuit package shelf 20.

このような構成において、電子回路パッケージlOを電
子回路パッケージシェルフ20に挿入する際に、まず電
子回路パッケージ10を予備挿入位置、すなわち電子回
路パッケージ10の手前側の上部および下部にある予備
挿入位置マーク10bと電子回路パッケージシェルフ2
0の挿入溝の前端とが一欽するところまで挿入し、この
とき電子回路パッケージ10に搭載されている発光タイ
万一ドIOCが点火すれば、電子回路パッケージ10が
正しい位k(列)に挿入されていることを示すので、そ
の1ま所屋の深さまで電子(ロ)路パッケージ10を挿
入する。もし、電子回路パッケージ10に?に載してい
る発光タイオードIOCが点灯しない場合は、電子回路
パッケージ10が正しい位置(タリ)に挿入されていな
いことを示すので、確社し、骸尚する位t(列)への電
子回路パッケージ10の再挿入を、同様にして行なう。
In such a configuration, when inserting the electronic circuit package IO into the electronic circuit package shelf 20, first insert the electronic circuit package 10 into the preliminary insertion position, that is, the preliminary insertion position marks on the upper and lower parts of the front side of the electronic circuit package 10. 10b and electronic circuit package shelf 2
If the light-emitting tie IOC mounted on the electronic circuit package 10 ignites at this time, the electronic circuit package 10 will be placed in the correct position k (column). Since it shows that it has been inserted, insert the electronic path package 10 to the depth of the hole. What if the electronic circuit package 10? If the light emitting diode IOC mounted on the column does not light up, it means that the electronic circuit package 10 is not inserted in the correct position (column). Reinsertion of package 10 is performed in the same manner.

(6)発明の詳細 な説明したように、本発明は従来の電子回路パッケージ
誤挿入防止&襖では、イロ」ら防ぐべき手段のなかった
ヒユーマン・ニジ−に!、61子回路パッケージの1挿
入に対して、電子(ロ)路パッケージの挿入位置(列)
の正−を口」視的に表示することによシ防止できる効果
が有る。
(6) As described in detail, the present invention prevents errors and errors that conventional electronic circuit package insertion prevention and sliding doors had no means to prevent. , the insertion position (column) of the electronic circuit package for one insertion of the 61 child circuit package.
Visually displaying the positive side of the problem has the effect of preventing it.

【図面の簡単な説明】[Brief explanation of the drawing]

第11ii!、lは従来の電子回路パッケージ娯挿入防
止機構を示す構造図、蕗2因は本発明による電子回路パ
ッケージ誤挿入防止機構〇一実施例を示す回路図、I@
3図は本発明による電子回路パッケージ誤挿入防止機構
の一実施例を示す構造図である。 1.10・・・電子回路パッケージ、11・・・電子回
路パッケージ品名表示、2.20・・・電子(ロ)路バ
ッケージシェルフ、21・・・列番号表示ラベル、22
・・・電子回路パッケージ品名六示ラベル、3.30・
・・バックボード、10a・・・接触ラント、10b・
・・予伽挿入位徽マーク、10C・・・発光ダイえ−ド
15・・・ジャンパ&m、20a・・・接触バネ、30
a・・・を源(+5V)、30b・・・接地(E)、3
5・・・ネジ振絖。
11th ii! , 1 is a structural diagram showing a conventional electronic circuit package insertion prevention mechanism, and 2 is a circuit diagram showing an embodiment of the electronic circuit package incorrect insertion prevention mechanism according to the present invention.
FIG. 3 is a structural diagram showing an embodiment of the electronic circuit package erroneous insertion prevention mechanism according to the present invention. 1.10...Electronic circuit package, 11...Electronic circuit package product name display, 2.20...Electronic circuit package shelf, 21...Column number display label, 22
・・・Electronic circuit package product name label, 3.30・
...Backboard, 10a...Contact runt, 10b.
...Yokai insertion position mark, 10C...Light-emitting diode 15...Jumper & m, 20a...Contact spring, 30
a... source (+5V), 30b... ground (E), 3
5...Screw thread.

Claims (1)

【特許請求の範囲】 n撫、m枚の電子回路パッケージ群と、これらの電子回
路パッケージ群を搭載する電子回路パッケージシェルフ
およびこれらの電子回路パッケージ群間の伽号麹を相互
接続するバックボードから構成される装置 路パッケージを電子回路パッケージシェルフにおける皺
当位置へ挿入する際該当位置以外へ誤挿入された時、可
視懺示器を点滅する手段を設けたことを4Illkとす
る可視方式による電子回路パッケージ誤挿入防止機構。
[Claims] From n and m electronic circuit package groups, an electronic circuit package shelf on which these electronic circuit package groups are mounted, and a backboard that interconnects these electronic circuit package groups. 4Illk is an electronic circuit based on a visible method, which is provided with a means for blinking a visible indicator when a device path package is inserted into a crease position on an electronic circuit package shelf and is incorrectly inserted into a position other than the corresponding position. Mechanism to prevent incorrect package insertion.
JP21527681A 1981-12-25 1981-12-25 Electronic circuit package erroneous insertion preventing mechanism by visual system Pending JPS58112400A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21527681A JPS58112400A (en) 1981-12-25 1981-12-25 Electronic circuit package erroneous insertion preventing mechanism by visual system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21527681A JPS58112400A (en) 1981-12-25 1981-12-25 Electronic circuit package erroneous insertion preventing mechanism by visual system

Publications (1)

Publication Number Publication Date
JPS58112400A true JPS58112400A (en) 1983-07-04

Family

ID=16669625

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21527681A Pending JPS58112400A (en) 1981-12-25 1981-12-25 Electronic circuit package erroneous insertion preventing mechanism by visual system

Country Status (1)

Country Link
JP (1) JPS58112400A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH038492U (en) * 1989-06-13 1991-01-28

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH038492U (en) * 1989-06-13 1991-01-28

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