JPS58123721A - Impurity doping method onto semiconductor crystal - Google Patents

Impurity doping method onto semiconductor crystal

Info

Publication number
JPS58123721A
JPS58123721A JP57007115A JP711582A JPS58123721A JP S58123721 A JPS58123721 A JP S58123721A JP 57007115 A JP57007115 A JP 57007115A JP 711582 A JP711582 A JP 711582A JP S58123721 A JPS58123721 A JP S58123721A
Authority
JP
Japan
Prior art keywords
semiconductor crystal
impurity doping
mask
doping
doping method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57007115A
Other languages
Japanese (ja)
Inventor
Toshiki Ehata
敏樹 江畑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP57007115A priority Critical patent/JPS58123721A/en
Publication of JPS58123721A publication Critical patent/JPS58123721A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00Ion implantation into wafers, substrates or parts of devices
    • H10P30/20Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping

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  • Thyristors (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は半導体素子での不純物ドーピング技術の改良に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in impurity doping techniques in semiconductor devices.

ダイオード、トランジスタおよび集積回路の製造におい
て、半導体結晶の所定の領域に選択的に所定の不純物を
拡散またはイオン注入によってドーピングする技術は最
も基礎的で重要なものである。所定の領域にのみ不純物
をドープするには、イオン注入法と拡散法とがある。例
えばイオン注入においては、フォトレジストをウェーバ
に塗布後、フォトレジストの窓を所定領域に設け、この
窓を通してイオン注入を行うのが最も普通である。
In the manufacture of diodes, transistors, and integrated circuits, the most basic and important technique is to selectively dope a predetermined region of a semiconductor crystal with a predetermined impurity by diffusion or ion implantation. There are ion implantation methods and diffusion methods for doping only a predetermined region with impurities. For example, in ion implantation, it is most common to apply photoresist to a wafer, then provide a photoresist window in a predetermined area, and perform ion implantation through this window.

拡散においてはマスク材に5ins、 Si @N4等
が通常用いられていて、このマスク材の窓からの拡散を
利用している。
For diffusion, a mask material such as 5ins, Si@N4, etc. is normally used, and diffusion through the window of this mask material is utilized.

いずれにせよドーピングのマスクは、正確に所定の位置
に窓が開けられていなければならないが、従来の方法に
おいては、どれだけ正確に所定領域の位置に窓開けが可
能かは、フォトマスクのパターンをフォトレジストに露
光転写する際の位置合わせ精度によって決まるが、従来
の露光装置では±1μmが限界であり、これ以上の精度
を得るのは困難であった。近年半導体素子の高周波特性
の向上、集積度の向上への要求は、ますます強くなって
いるが、この要求を満すには、素子の大きさを小さくす
る必要があり、そのため不純物のドーピングにおいても
より微小な領域に高精度の位置合わせで行うことが、ま
すます強く求められている。
In any case, the doping mask must have windows formed at precisely predetermined positions, but in conventional methods, the pattern of the photomask depends on how accurately the windows can be opened at the positions of the predetermined areas. It is determined by the positioning accuracy when exposing and transferring the image to the photoresist, but with conventional exposure equipment, the limit is ±1 μm, and it has been difficult to obtain higher accuracy. In recent years, the demand for improved high-frequency characteristics and increased integration of semiconductor devices has become stronger and stronger, but in order to meet these demands, it is necessary to reduce the size of the devices. There is an increasing demand for highly accurate positioning in even smaller areas.

本発明は、このような状況を鑑みなされたものであり±
1μm以下の高精度の位置合わせて2種類の不純物のド
ーピングを行うことを目的とするものである。
The present invention was made in view of this situation.
The purpose is to perform doping with two types of impurities with highly accurate alignment of 1 μm or less.

以下に図を用いて詳細に本発明の説明を行う。The present invention will be explained in detail below using figures.

第1図において1は半導体結晶、例えば半絶縁性GaA
s結晶基板である。基板表面上に形成したマスクパター
ン3を用いてイオン注入により不純物をドーピングし導
電型領域2を形成する。実施例では厚さ1.5μmの7
オトレジストを通常のりソグラフィでパターン形成しマ
スクパターン8とした。
In FIG. 1, 1 is a semiconductor crystal, for example semi-insulating GaA
s crystal substrate. A conductive type region 2 is formed by doping impurities by ion implantation using a mask pattern 3 formed on the surface of the substrate. In the example, 7 with a thickness of 1.5 μm
A mask pattern 8 was formed by forming a pattern on the photoresist using ordinary glue lithography.

またイオン注入条件としては200KeVの注入エネル
ギーで6X101’ドーターのSiイオンを注入した。
As for the ion implantation conditions, 6×101' daughter Si ions were implanted with an implantation energy of 200 KeV.

この結果深さ0.17μmの位置に濃゛度3.2X10
1マ/ffi ”のピークを有する導電型領域を得た。
As a result, the density was 3.2×10 at a depth of 0.17 μm.
A conductivity type region having a peak of 1 mm/ffi'' was obtained.

次いで第2図に示す様に試料全面に薄膜4′を形成しマ
スク用パターン3を除去し、第3図に示すようなマスク
用パターン4を得る。実施例では真空蒸着法によって厚
さ0.3μmのS i Os膜を試料全面に堆積させア
セトンによって7オトレジストパターン8を除去した。
Next, as shown in FIG. 2, a thin film 4' is formed on the entire surface of the sample, and the mask pattern 3 is removed to obtain a mask pattern 4 as shown in FIG. In the example, a 0.3 μm thick SiOs film was deposited on the entire surface of the sample by vacuum evaporation, and 7 photoresist patterns 8 were removed with acetone.

この徒弟2の不純物ドーピングを行ない新たな導電型領
域2′を形成する。例えば注入エネルギ50KeV、注
入量1.8XIQtsドーズ/ffi”のSiイオンを
注入し深さ0.04μm の位置に濃度2X 10 ”
α8のピークを有する導電型領域2′を得た。最後に注
入元素をアニールによって活性化することにより2種類
の導電型領域をもつ不純物ドーピングが実現する。
This apprentice 2 is doped with impurities to form a new conductivity type region 2'. For example, Si ions are implanted with an implantation energy of 50KeV and an implantation amount of 1.8XIQts dose/ffi", and a concentration of 2X 10" is implanted at a depth of 0.04μm.
A conductivity type region 2' having a peak of α8 was obtained. Finally, by activating the implanted element by annealing, impurity doping with two types of conductivity type regions is realized.

本発明においては、マスク用パターンを正逆反転させて
不純物をドーピングすることが本質的な要素であり、そ
の結果何ら高度な位置合わせをせずに第8図に示すよう
に互いに接する導電型領域が形成されることが特徴であ
る。これらの導電型領域はアニール等の高温処理によっ
て横方向へ拡がるため自、動的に重なるため、電気的接
続は容易に得られる。
In the present invention, the essential element is to dope the impurity by reversing the mask pattern, and as a result, the conductivity type regions are in contact with each other as shown in FIG. 8 without any advanced alignment. It is characterized by the formation of These conductivity type regions are expanded laterally by high temperature treatment such as annealing and automatically and dynamically overlap, so that electrical connection can be easily obtained.

明らかに本発明は上記例以外にも各種の変形、応用が可
能である。−えば3のフォトレジストはTi、 Mo、
 Ta、 At等の高精度エツチングが可能な他の釡属
、あるいはS i Os等の無機化合物系あるいはポリ
イミド等の有機物系の絶縁物を用いることもできる。
Obviously, the present invention can be modified and applied in various ways other than the above examples. -For example, photoresist 3 is made of Ti, Mo,
Other metals that can be etched with high precision, such as Ta and At, or insulators made of inorganic compounds such as SiOs, or organic compounds such as polyimide may also be used.

また4′の薄膜はイオン注入や熱拡散のマスクとなり、
かつ3のマスクが選択的に除去し得る材料であれば本発
明の要件を!たす。このため任意の材料及び形成法が可
能である。例えば酸化シリコン、窒化シリコン、酸化ア
ルミニウム、窒化アルミニウム、酸化ジルコニウム、酸
化チタン等の無機化合物膜、At、 T i 、 W、
 Mo 等の金属膜なt+’Lそれらを陽極酸化法等で
絶縁膜化した膜が可能である。また、ドープする不純物
はSiに限定されず、N型、P型任意のものを採用でき
、かつマスク材との組合せにより熱拡散等地の不純物ド
ーピング法も可能である。また結晶はGaAsに限定さ
れずにSi、 Ge、 InP等任章のものを用いるこ
とができる。
In addition, the thin film 4' serves as a mask for ion implantation and thermal diffusion.
And if the mask in step 3 is made of a material that can be selectively removed, this meets the requirements of the present invention! Tasu. For this purpose, any material and formation method are possible. For example, inorganic compound films such as silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, zirconium oxide, titanium oxide, At, Ti, W,
It is possible to use a metal film such as Mo or the like, which is made into an insulating film by an anodic oxidation method or the like. Further, the impurity to be doped is not limited to Si, but any N-type or P-type impurity can be used, and in combination with a mask material, other impurity doping methods such as thermal diffusion are also possible. Further, the crystal is not limited to GaAs, and materials such as Si, Ge, and InP can be used.

以上述べた如く本発明によれば、最初の7ぐターンに対
して第1回目のドーピングを行った後、前記パターンの
位置関係を保持したままで第2回目のドーピングを行っ
ているため、第1回目を第2回目のドーピングの相対位
置を極めて精密に設定することが出来るため、互いに深
さ、濃度、導伝型などが異なった二つの導伝層を、隣接
して高精度の合わせ精度で形成することができる。
As described above, according to the present invention, after the first doping is performed for the first seven turns, the second doping is performed while maintaining the positional relationship of the patterns. Because the relative positions of the first and second doping can be set extremely precisely, two conductive layers with different depths, concentrations, conductivity types, etc. can be placed adjacent to each other with high accuracy. can be formed with.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第8図は本発明の一実施例を示すための断面
図である。 1・・・半導体結晶基板 2・・・−導電型領域 2′・・・第2の導電型領域 3・・・マスク材料 4・・・1マスク/パターン 4′・・・マスク用薄膜
1 to 8 are cross-sectional views showing one embodiment of the present invention. 1...Semiconductor crystal substrate 2...-Conductivity type region 2'...Second conductivity type region 3...Mask material 4...1 Mask/pattern 4'...Thin film for mask

Claims (1)

【特許請求の範囲】[Claims] 11半導体結晶中に選択的に不純物をドーピングする方
法において、半導体結晶の表面にマスク材を形成し、こ
れをマスクとして第1回目”の不純物ドーピングを行な
い、かかる後に該マスク材と正逆反転したマスクパター
ンを形成した後、第2回目の不純物ドーピングを行なう
ことを特徴とする半導体結晶への不純物ドーピング法
11 In a method of selectively doping impurities into a semiconductor crystal, a mask material is formed on the surface of the semiconductor crystal, and this is used as a mask to perform the first impurity doping, and then the mask material is reversely reversed. An impurity doping method for semiconductor crystal characterized by performing a second impurity doping after forming a mask pattern
JP57007115A 1982-01-19 1982-01-19 Impurity doping method onto semiconductor crystal Pending JPS58123721A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57007115A JPS58123721A (en) 1982-01-19 1982-01-19 Impurity doping method onto semiconductor crystal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57007115A JPS58123721A (en) 1982-01-19 1982-01-19 Impurity doping method onto semiconductor crystal

Publications (1)

Publication Number Publication Date
JPS58123721A true JPS58123721A (en) 1983-07-23

Family

ID=11657084

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57007115A Pending JPS58123721A (en) 1982-01-19 1982-01-19 Impurity doping method onto semiconductor crystal

Country Status (1)

Country Link
JP (1) JPS58123721A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01268818A (en) * 1988-04-19 1989-10-26 Nippon Steel Corp Production of directly rolled thick steel plate

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5333053A (en) * 1976-09-09 1978-03-28 Toshiba Corp Production of semiconductor device
JPS5660015A (en) * 1979-10-22 1981-05-23 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5333053A (en) * 1976-09-09 1978-03-28 Toshiba Corp Production of semiconductor device
JPS5660015A (en) * 1979-10-22 1981-05-23 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01268818A (en) * 1988-04-19 1989-10-26 Nippon Steel Corp Production of directly rolled thick steel plate

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