JPS58123723A - Impurity doping method onto semiconductor crystal - Google Patents

Impurity doping method onto semiconductor crystal

Info

Publication number
JPS58123723A
JPS58123723A JP57007117A JP711782A JPS58123723A JP S58123723 A JPS58123723 A JP S58123723A JP 57007117 A JP57007117 A JP 57007117A JP 711782 A JP711782 A JP 711782A JP S58123723 A JPS58123723 A JP S58123723A
Authority
JP
Japan
Prior art keywords
mask
impurity doping
impurity
semiconductor crystal
doping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57007117A
Other languages
Japanese (ja)
Inventor
Toshiki Ehata
敏樹 江畑
Kenichi Kikuchi
健一 菊地
Hideki Hayashi
秀樹 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP57007117A priority Critical patent/JPS58123723A/en
Publication of JPS58123723A publication Critical patent/JPS58123723A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials

Landscapes

  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To dope impurity at positioning of high accuracy being less than + or -1mum, by a method wherein a mask material before becoming a compound is expanded in volume by a given ratio when it becomes a compound at a prescribed condition. CONSTITUTION:A first mask 4 is formed on a surface of a semiconductor crystal 1 and first impurity doping is performed, thereby a first impurity doping layer 2 is formed. A metal film 3 is formed on whole surface by means of vacuum evaporation. The mask 4 is removed and a second mask 3' is obtained. Second impurity doping is performed using the mask 3'. Al mask 3'' is obtained by expansion and required impurity doping of third time is performed using the Al mask 3'', thereby n<+> region 2'' is selectively formed. Finally, injection element is annealed and activated, thereby the impurity doping is completed.

Description

【発明の詳細な説明】 本発明は半導体素子製造における不純物ドーピング技術
の改良に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improvements in impurity doping techniques in semiconductor device manufacturing.

ダイオード、トランジスタおよび集積回路の製造におい
て、半導体結晶の所定の領域、に選択的に所定の不純物
を拡散またはイオン注入によってドーピングする技術は
最も基礎的で重要なものである。所定の領域にのみ不純
物をドープするには。
In the manufacture of diodes, transistors, and integrated circuits, the most basic and important technique is to selectively dope a predetermined region of a semiconductor crystal with a predetermined impurity by diffusion or ion implantation. To dope impurities only in predetermined areas.

イオン注入法と拡散法とがある。例えばイオン注入にお
いては、フォトレジストをウェーハーに塗布後フォトレ
ジストの窓を所定領域に設ケ、コノ窓を通ってイオン注
入を行うのが最も普通である。
There are ion implantation methods and diffusion methods. For example, in ion implantation, it is most common to apply photoresist to a wafer, then provide a photoresist window in a predetermined area, and then implant ions through the window.

拡散においてはマスク材に5ins、 51mN4等が
通常用いられていてこのマスク材の窓からの拡散を利用
している。
For diffusion, 5ins, 51mN4, etc. are normally used as a mask material, and the diffusion through the windows of this mask material is utilized.

いずれにせよドーピングのマスク−は正確に所定の位置
に窓が開けられていなければならないが、従来の方法に
おいてはどれだけ正確に所定領域の位置に窓開けが可能
かは、フォトマスクのパターンを7オトレジストに露光
転写する際の位置合わせ精度によって決まり、従来の露
光装置では±1μmが限界であり、これ以上の精度を得
るのは困難であった。そして近年半導体素子の高周波特
性の向上、集積度の向上への要求はますます強くなって
いるが、この要求を満すには素子の大きさを小さくする
必要があり、そのため不純物のドービングにおいてもよ
り微小な領域に高精度の位置合わせで行うことがますま
す強く求められている。
In any case, the doping mask must have windows formed at precisely predetermined positions, but in conventional methods, how accurately it is possible to open windows at the positions of predetermined areas depends on the pattern of the photomask. It is determined by the positioning accuracy during exposure transfer to the 7-photoresist, and with conventional exposure equipment, the limit is ±1 μm, and it has been difficult to obtain higher accuracy. In recent years, there has been an increasingly strong demand for improved high-frequency characteristics and higher integration of semiconductor devices, but in order to meet these demands, it is necessary to reduce the size of the devices. There is an increasing demand for highly accurate positioning in smaller areas.

本発明はこのような状況を鑑みなされたものであり、±
1μm以下の高精度の位置合わせて不純物のドーピング
を行うことを目的とするものである。
The present invention was made in view of this situation, and ±
The purpose is to perform impurity doping with highly accurate positioning of 1 μm or less.

以下に図を用いて詳細に本発明の説明を行う。The present invention will be explained in detail below using figures.

第1図において、lは半導体結晶、例えば半絶縁性Ga
As結晶基板である。かかる半導体結晶表面上にまず第
1のマスク4を形成し、・第1回目の不純物ドーピング
を行ない第1の不純物ドーピング層2を形成する。例え
ばSeのイオン注入により浅いn型領域を形成する。マ
スク4としては1.5μm厚の7オトレジストを通常の
りソグラフィでパターニングすることにより形成した。
In FIG. 1, l is a semiconductor crystal, for example a semi-insulating Ga
It is an As crystal substrate. First, a first mask 4 is formed on the surface of the semiconductor crystal, and a first impurity doping is performed to form a first impurity doped layer 2. For example, a shallow n-type region is formed by ion implantation of Se. The mask 4 was formed by patterning a 1.5 .mu.m thick photoresist using normal gluing lithography.

次いで第2図のように全面に3の金属膜例えば0.8μ
m厚のAt層を真空蒸着により形成する。この後4の第
1のマスクを例えばアセトンで除去すると第8図のよう
な第2のマスク3′を得る。このマスク3′を用いて第
2回目の不純物ドーピングを行なう。例えばSeのイオ
ン注入により第1の不純物層2よりも深いn型領域2′
を形成する。次いでAtマスク3′を陽極酸化法等によ
り膨張させてktマスクパターン3″を形成する(第4
図)。陽極酸化法のように表面を酸化ないし窒化等で絶
縁化する場合、一般に形成された絶縁膜の厚さの半分だ
け外側へ膨張する。
Next, as shown in Figure 2, a metal film of 3, for example 0.8μ, is applied to the entire surface.
An m-thick At layer is formed by vacuum evaporation. Thereafter, the first mask 4 is removed using, for example, acetone to obtain a second mask 3' as shown in FIG. A second impurity doping is performed using this mask 3'. For example, an n-type region 2' deeper than the first impurity layer 2 is formed by ion implantation of Se.
form. Next, the At mask 3' is expanded by anodic oxidation or the like to form a kt mask pattern 3'' (fourth
figure). When the surface is insulated by oxidation or nitridation as in the case of anodic oxidation, the insulating film generally expands outward by half the thickness of the formed insulating film.

ここではAtマスク3′を0.25 gn陽極酸化し4
スク3′を両側へそれぞれ02Spmずつ膨張させた。
Here, the At mask 3' is anodized with 0.25 gn 4
The disk 3' was expanded by 02 Spm on each side.

この後膨張したAtマスク3″をマスクとして所望の第
3回目の不純物ドーピングを例えばS9のイオン注入に
よりn十層領域2″を選択的に形成する(第4図)。
Thereafter, using the expanded At mask 3'' as a mask, desired third impurity doping is performed, for example, by ion implantation of S9 to selectively form the n0 layer region 2'' (FIG. 4).

最後にアニールによって注入元素の活性化を行ない不純
物ドーピングを終わる。ここでさらに第1回目の不純物
ドーピング後に半導体結晶及びAtマスク8′の表面に
絶縁性薄膜を形成し陽極酸化に対して半導体結晶表面を
保護することも可能である。
Finally, the implanted elements are activated by annealing to complete the impurity doping. Here, it is also possible to further protect the semiconductor crystal surface against anodic oxidation by forming an insulating thin film on the surface of the semiconductor crystal and the At mask 8' after the first impurity doping.

この時マスク8′の陽極酸化は側面のみ進行し、側面方
向をこのみ膨張したAtマスク8″を得る。本発明はマ
スクが側面方向に膨張すればその目的を満たすものであ
り両実施例とも得られる効果は同じものとなる。
At this time, the anodic oxidation of the mask 8' progresses only on the side surfaces, yielding an At mask 8'' that expands in the lateral direction.The purpose of the present invention is achieved if the mask expands in the lateral direction, and both embodiments can be obtained. The effect will be the same.

本実施例では2回目のイオン注入が1回目のイオン注入
よりも深く、すなわち高エネルギで、1回目よりも低い
ドーズ量で行われた場合のものであり、2のn型領域と
2″のn十領域との間に2′の深いn型領域を介在させ
た構造を得る例である。ここで2と2″との間隔はAt
マスク3′と膨張したAtマスクぎ′とのパターンサイ
ズ差すな、ゎち表面酸化によるパターン膨張量によって
決定されるが、Azは例えば陽極酸化、プラズマ陽極酸
化等により高精度の膨張が可能であるため、その量を±
1μm以下で制御することができ、従って2と2″との
間隔は高精度で制御できる。
In this example, the second ion implantation was performed deeper than the first ion implantation, that is, with high energy and at a lower dose than the first, and the n-type region 2 and the 2" This is an example of obtaining a structure in which a 2' deep n-type region is interposed between the n0 region.Here, the distance between 2 and 2" is At
The pattern size difference between the mask 3' and the expanded At mask 3' is determined by the amount of pattern expansion due to surface oxidation, but Az can be expanded with high precision by, for example, anodic oxidation, plasma anodization, etc. Therefore, the amount is ±
It can be controlled to within 1 μm, and therefore the spacing between 2 and 2″ can be controlled with high precision.

明らかに本発明は上記例以外にも各種の変形、応用が可
能である。例えば8のAtはTi、 Mo、 Ta等の
高精度陽極酸化が可能な他の金属、あるいはSi等の半
導体材料を用いることもできる。広くは酸化物のみなら
ず窒化物や炭化物等の他の化合物を表面に形成できる材
料であればよい。この時第1のマスク材は3の材料に対
して選択的に除去し得るものであればよくフォトレジス
トに何ら限定されるものでない。またドープする不純物
はSeに限定されず、n型、p型任意のものを採用でき
る。また結晶はGaAsに限定されずにSi、 Ge、
 InP等任意のものを用いることができる。
Obviously, the present invention can be modified and applied in various ways other than the above examples. For example, for At in No. 8, other metals that can be anodized with high precision such as Ti, Mo, and Ta, or semiconductor materials such as Si can also be used. Broadly speaking, any material that can form not only oxides but also other compounds such as nitrides and carbides on the surface may be used. At this time, the first mask material is not limited to photoresist as long as it can be selectively removed with respect to the third material. Further, the impurity to be doped is not limited to Se, and any n-type or p-type impurity can be used. Moreover, the crystal is not limited to GaAs, but also Si, Ge,
Any material such as InP can be used.

以上述べた如く本発明によれば、At金属の如く化合物
となる前の段階のマスク材において所定の条件で化合物
とすることにより体積が所定の割合で膨張することを利
用するために、膨張前後のマスクをもとにドーピングを
行うと極めて高精度な間隔差を持ったドーピングが可能
と゛なる。加えて2つのドーピングのマスクとして同一
パターンの正逆反転したものを用いるため、互いに接し
たドーピング層が形成され、位置関係の極めて高精度な
、互いに深さ、濃度、導伝型の少なくとも一つが異なる
8種類の不純物ドーピングが実現する。
As described above, according to the present invention, in order to take advantage of the fact that the volume of a mask material at a stage before it becomes a compound, such as At metal, expands at a predetermined rate when it is made into a compound under predetermined conditions, If doping is performed based on this mask, it becomes possible to perform doping with extremely high precision spacing differences. In addition, since two doping masks are used with the same pattern reversed, doping layers that are in contact with each other are formed, and the positional relationship is extremely precise and at least one of depth, concentration, and conductivity is matched. Eight different types of impurity doping are realized.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第4mは本発明の製造方法の工程を示すため
の断面図である。 1・・・半導体結晶基板、2・・・第1不純物ドープ領
域、3,3′・・・マスク材料 例えばA/。
1 to 4m are cross-sectional views showing the steps of the manufacturing method of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor crystal substrate, 2... First impurity doped region, 3, 3'... Mask material For example, A/.

Claims (1)

【特許請求の範囲】[Claims] (1)半導体結晶中に選択的に不純物をドーピングする
方法において、半導体結晶の表面に第1のマスク材を形
成し、これをマースフとして第1回目の不純物ドーピン
グを行ない、第1のマスク材と正逆反転した金属等から
なる。第2のマスクを形成して第2回目の不純物ドーピ
ングを行ない、次いで第2のマスク材を化合物に変化せ
しめることにより所定量膨張させた後に第8回目の不純
物ドーピングを行なうことを特徴とする半導体結晶への
不純物ドーピング方法。
(1) In a method of selectively doping impurities into a semiconductor crystal, a first mask material is formed on the surface of the semiconductor crystal, and the first impurity doping is performed using this material as MarsF. It is made of metal, etc. that has been reversed. A semiconductor characterized in that a second mask is formed and a second impurity doping is performed, and then the second mask material is changed into a compound to expand it by a predetermined amount, and then an eighth impurity doping is performed. Method of doping impurities into crystals.
JP57007117A 1982-01-19 1982-01-19 Impurity doping method onto semiconductor crystal Pending JPS58123723A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57007117A JPS58123723A (en) 1982-01-19 1982-01-19 Impurity doping method onto semiconductor crystal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57007117A JPS58123723A (en) 1982-01-19 1982-01-19 Impurity doping method onto semiconductor crystal

Publications (1)

Publication Number Publication Date
JPS58123723A true JPS58123723A (en) 1983-07-23

Family

ID=11657137

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57007117A Pending JPS58123723A (en) 1982-01-19 1982-01-19 Impurity doping method onto semiconductor crystal

Country Status (1)

Country Link
JP (1) JPS58123723A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5378181A (en) * 1976-12-22 1978-07-11 Hitachi Ltd Semiconductor device and its manufacture
JPS54112165A (en) * 1978-02-22 1979-09-01 Seiko Epson Corp Manufacture of semiconductor integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5378181A (en) * 1976-12-22 1978-07-11 Hitachi Ltd Semiconductor device and its manufacture
JPS54112165A (en) * 1978-02-22 1979-09-01 Seiko Epson Corp Manufacture of semiconductor integrated circuit

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